From nobody Mon Sep 28 16:22:29 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBE9936DA14; Wed, 19 Aug 2026 19:47:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787168829; cv=none; b=V8q6Q8YAWH1Ulr6gk+1xvMWYTfe/OfR/ZrBPEZgJ5vMGAeByrapnKEV40AgkzjCTbv4sIBqOnFrkPqNOODamwtOuVhAamSwcOIFNsYZ7pkhiq+d2njC6Da+B03UlNqMNBZJZY0of41GzppQdSCBQmLshVLpVI15iKlJ4lQh2UVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787168829; c=relaxed/simple; bh=NMxzzIjyFfO1Bxo7DNmoceDm6HdGaRGoAgq7Bo+1ddI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=re7TyR1TYNnumJ9fJxTZ01WWrzfvxpsylGWixCXX1CmLQCq9Y1+3vJI+U0ke+7HI14CX9ONLvlrJDg9OidgcH5AMYbldjO/HKGriKULUCrHHfH/Wt2XoErE9Tq4XaMM+F4tRXFssjDuo9UCrcj3JZEhedTXEJQVFkPeAHWf2++A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NlzvAsph; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XFWIddU6; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NlzvAsph"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XFWIddU6" Date: Wed, 19 Aug 2026 19:47:04 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1787168826; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=O100J9DvSyOkF4jPK30jjQCIUsVCSupHQQKIRuGkp+4=; b=NlzvAsphhmgC/FBwLw1qGSISJNxdN3JKTid/W9GFT/FrjyFV03rfSOE1kyTPF+5T/hb8d1 YhBEpTouQ+Ue389KhM5Sc/RJOGYhQ1YrrTo6cY6fjs/yM4YcR5gt+y3RcscA6riWD5WZQ1 iAKk8Lv1y1OCymPdB2njFoxCF2AvP+1a9UGHlpQ0NwOEoqdUGlGvvnPA5nQU+9FH+Rt9iw yL5hF2jOK8DLJc7UPqYMB9UHk2OOVC4X1Usnb/tHuUIUiE7SA7PYuFAN9cHKiMP+DK8pTQ AgbAwxpYWBY+7XxL+vqc4iYFGDzLwiPJJSblnZOpWB7wwBAn1da6EyHBQ7Gt6g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1787168826; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=O100J9DvSyOkF4jPK30jjQCIUsVCSupHQQKIRuGkp+4=; b=XFWIddU6wZkCCWTznjrbkFBos5F4sx+Pe2HtNQZfY67XQvVaPKydoCp3zXQoWbvSOGK3Mj 99iVOwjzoHF9zFDQ== From: "tip-bot2 for Biju Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/urgent] irqchip/renesas-rzg2l: Fix loss of interrupt Cc: Biju Das , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20260818110937.5816-1-biju.das.jz@bp.renesas.com> References: <20260818110937.5816-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178716882463.1542179.15899707442683610026.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/urgent branch of tip: Commit-ID: 50b10bd0c2d721ad38abd1abe3acdefb6caa0944 Gitweb: https://git.kernel.org/tip/50b10bd0c2d721ad38abd1abe3acdefb6= caa0944 Author: Biju Das AuthorDate: Tue, 18 Aug 2026 12:09:33 +01:00 Committer: Thomas Gleixner CommitterDate: Wed, 19 Aug 2026 21:40:13 +02:00 irqchip/renesas-rzg2l: Fix loss of interrupt rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=3D0 353=3D0 328=3D0 352=3D0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register. Since 1-bits are left unchanged by hardware, concurrently-set status bits for other interrupts are preserved. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260818110937.5816-1-biju.das.jz@bp.renesas= .com --- drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index f6b2e69..b3774f8 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -161,7 +161,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv = *priv, unsigned int hwirq * falling/rising-edge. */ if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { - writel_relaxed(iscr & ~bit, priv->base + ISCR); + writel_relaxed(~bit, priv->base + ISCR); /* * Enforce that the posted write is flushed to prevent that the * just handled interrupt is raised again. @@ -177,7 +177,7 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv= *priv, unsigned int hwir =20 reg =3D readl_relaxed(priv->base + TSCR); if (reg & bit) { - writel_relaxed(reg & ~bit, priv->base + TSCR); + writel_relaxed(~bit, priv->base + TSCR); /* * Enforce that the posted write is flushed to prevent that the * just handled interrupt is raised again.