From nobody Wed Sep 30 09:44:41 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 956A54570DA; Wed, 12 Aug 2026 14:11:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786543889; cv=none; b=kyKly4SyuE9Hp7nniG1QkS15wzYR7tS1D2hgExY7mLQrc25iKs49NHmxquMIISg8zuTfcC4jEvSVdjLol8xhUnFoU3IVWS8vtm+DJ+gjicTPGcfJryAuKDu5J7p2LISRJyrvJ7QAu01m6eeDXe7PhNLsfj/tPtOKy0GLmrWeddQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786543889; c=relaxed/simple; bh=N8GrGxkAoitaJ9sOlgnOp1xduybGb1sDYoKgDLQkeYo=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=GJNpzttp6Hgd/XcqRKrLOl9VTmkqRy8CLpBvqNQ1wW1gTph4M0V+5myCMkjlCGF9WpKvBue63Ygl8xbiF0ZsYibfhoxTIay5h4bNDn0fuurHNAMRXP0XYn0DKpne63qNWW3ILFEzO2vh96q4skjwZ1ghg14R5ZEexjyn1dKtBvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Af/z+vQr; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oP6YOrbQ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Af/z+vQr"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oP6YOrbQ" Date: Wed, 12 Aug 2026 14:11:24 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1786543886; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+LOgi4Ve0ZPGvqXB+R1WHTwHg22Zv4CszXoQc+DO6tk=; b=Af/z+vQri3IvW9Nuc6fphKSzLRhQpd7iPz3YpTNfnja6IEyLXWombQKiXkAG1pEjEEKwm2 XF7sB12C+070/inzuqIx6P4G17Uv8LP6Ua0YMIYuqsgpVbhx+GPlld4RzgVK2xlGIVg1+s RKFfObLtBWpA3Jtzvx24eo3cYsEUqSe1EI/kXu1BbYm9323jaQGNaC4x9t2gOiQu0gil9R VUnepmSg5YJ3ZfpW36UBf5VbWkQblR8XTIX0Z7vfma+QPSz48/e2KIzIkqiJtqawNrQ/w3 osRJsM9DppKKdaIS1HzSwdle6d8mprJw6vM9nhOs/5+8Qusurwa5SFsC6sh3xA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1786543886; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+LOgi4Ve0ZPGvqXB+R1WHTwHg22Zv4CszXoQc+DO6tk=; b=oP6YOrbQpwrciDt6vkJy1mhgFrq/PXnrzhRpedc6LfW7hOo+Tkt0E+4Hoo/wN+ZdTBysmk mC19LYzVws1XZMCQ== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , Thomas Falcon , Zide Chen , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260717080342.1879573-5-dapeng1.mi@linux.intel.com> References: <20260717080342.1879573-5-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178654388461.442315.12524346721377197540.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 85182f902afda28ca7ae3408b72f31640a5cfc73 Gitweb: https://git.kernel.org/tip/85182f902afda28ca7ae3408b72f31640= a5cfc73 Author: Dapeng Mi AuthorDate: Fri, 17 Jul 2026 16:03:38 +08:00 Committer: Peter Zijlstra CommitterDate: Mon, 10 Aug 2026 15:05:47 +02:00 perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails intel_pmu_cpu_prepare() allocates per-CPU perf state first and then sets up the arch PEBS buffer. If alloc_arch_pebs_buf_on_cpu() fails, the previously allocated cpuc resources are left behind. Make the failure path call intel_cpuc_finish(cpuc) to release the per-CPU state allocated by intel_cpuc_prepare(). Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Thomas Falcon Reviewed-by: Zide Chen Link: https://patch.msgid.link/20260717080342.1879573-5-dapeng1.mi@linux.in= tel.com --- arch/x86/events/intel/core.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a991fc4..b47d2f0 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5924,13 +5924,20 @@ err: =20 static int intel_pmu_cpu_prepare(int cpu) { + struct cpu_hw_events *cpuc =3D &per_cpu(cpu_hw_events, cpu); int ret; =20 - ret =3D intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); + ret =3D intel_cpuc_prepare(cpuc, cpu); if (ret) return ret; =20 - return alloc_arch_pebs_buf_on_cpu(cpu); + ret =3D alloc_arch_pebs_buf_on_cpu(cpu); + if (ret) { + intel_cpuc_finish(cpuc); + return ret; + } + + return 0; } =20 static void flip_smm_bit(void *data)