From nobody Tue Sep 29 04:46:55 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14D082EBB8C; Wed, 12 Aug 2026 14:11:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786543886; cv=none; b=AgudGQP9Tl/FQcfdbcexwbLwt794HwNOezKl8mD70wahdPppwiMCql2OnYsIampvzKzAQu8FMrWPascy2VhMMN00AWHUKeOML0qzEcR393s52z0PxraFBkUbJXX8ndMKQIJdHDah5Fs1TxNbCU/Fi/3Td08kxoeS9rJMZ71qPnE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786543886; c=relaxed/simple; bh=YOP/BJVofMpu/a9zcIpvNZTc5J7GVm/4Cm3M1kOXUuo=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=G8nm6thnGt9DuzNNLcuchrbYvkZuf56vMpRKNSnOgo+4UXYRhWl2m3Rx0xB45u1KJuqeNmv2f129hhg2ImHyWDPoIK7wu7B4nYiiwwm6a4RGexRtUOb/Ipe33W6OXX5zqln0/sLF+XNJ9VX1oR5oQ/tRVkkWO8qEyN5fy25T840= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QXWt1Yph; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Ct4kN3Lm; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QXWt1Yph"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Ct4kN3Lm" Date: Wed, 12 Aug 2026 14:11:21 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1786543883; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PvEyyem3Sv8Pf/PfxTZB+5u5wKNIiy4ppJ012c0FVh8=; b=QXWt1YphnQY/KIYcLXVJkmdo4Z0msP9/WnkH5CHd1AzPX/j612zObA+FAZSNTRQG4CkZWK RpDpjAPnywnPFEXeLheg00mb2IVlREo+JrSwzNxzKcT9Sl/3i1vIlOYVD0K10AEy6xCMfq /dYfL2babStsL+jbLtbeFo1kP51l5UG/iS3wnRuT983nUHg5mx26DEdEdX06DxA629SXms eCveLgXEwYPMHTg7tU1ILwbJUlg74S6Jb70RR4mmGCmgDiTT9JmrDLx2VmYw4hp7C+TeXp cMlIOTXPFUGdJ0SSJciqcrwKQj71EOCoScG12edr4Yk+MUZyk3UAXj9WwUQw1w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1786543883; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PvEyyem3Sv8Pf/PfxTZB+5u5wKNIiy4ppJ012c0FVh8=; b=Ct4kN3LmNAt5nTXF5KtcH4wgT9hxwfJAh4c8LLNl3iBMkxH+zzHL88GE589GUZHGZ8c0dV t3ZlKDWowvHBslBQ== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Fix intel_cap handling on hybrid PMUs Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , Thomas Falcon , Zide Chen , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260717080342.1879573-7-dapeng1.mi@linux.intel.com> References: <20260717080342.1879573-7-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178654388168.442315.17212883665190608802.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: dd384d661f06e3725aad3a932a53e0ff81fb8805 Gitweb: https://git.kernel.org/tip/dd384d661f06e3725aad3a932a53e0ff8= 1fb8805 Author: Dapeng Mi AuthorDate: Fri, 17 Jul 2026 16:03:40 +08:00 Committer: Peter Zijlstra CommitterDate: Mon, 10 Aug 2026 15:05:48 +02:00 perf/x86/intel: Fix intel_cap handling on hybrid PMUs intel_cap (IA32_PERF_CAPABILITIES) updates are currently tied to X86_FEATURE_ARCH_PERFMON_EXT, but these are independent feature paths. As a result, hybrid PMU capability state can be updated under the wrong condition. Also, intel_pmu_broken_perf_cap() is too narrow. Per RPL018, the missing PERF_METRICS_AVAILABLE bit affects both Raptor Lake and Meteor Lake parts, not only the currently covered subset. Move intel_cap updates out of the ARCH_PERFMON_EXT-gated path, extend intel_pmu_broken_perf_cap() coverage to both RPL and MTL families, and introduce intel_update_pmu_caps() to centralize PMU capability updates. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Thomas Falcon Reviewed-by: Zide Chen Link: https://patch.msgid.link/20260717080342.1879573-7-dapeng1.mi@linux.in= tel.com --- arch/x86/events/intel/core.c | 40 +++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c418176..f6ee181 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6147,8 +6147,14 @@ static void intel_pmu_check_extra_regs(struct extra_= reg *extra_regs); =20 static inline bool intel_pmu_broken_perf_cap(void) { - /* The Perf Metric (Bit 15) is always cleared */ - if (boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE || + /* + * The Perf Metric (Bit 15) is always cleared on P-core of + * RPL and MTL. Details can be found in RPL018 erratum. + */ + if (boot_cpu_data.x86_vfm =3D=3D INTEL_RAPTORLAKE || + boot_cpu_data.x86_vfm =3D=3D INTEL_RAPTORLAKE_P || + boot_cpu_data.x86_vfm =3D=3D INTEL_RAPTORLAKE_S || + boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE || boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE_L) return true; =20 @@ -6183,7 +6189,7 @@ static inline void __intel_update_large_pebs_flags(st= ruct pmu *pmu) =20 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX= _FIXED)) =20 -static void update_pmu_cap(struct pmu *pmu) +static void update_pmu_cap_from_perfmonext(struct pmu *pmu) { unsigned int eax, ebx, ecx, edx; union cpuid35_eax eax_0; @@ -6241,10 +6247,24 @@ static void update_pmu_cap(struct pmu *pmu) WARN_ON(x86_pmu.arch_pebs =3D=3D 1); x86_pmu.arch_pebs =3D 0; } +} + +static void intel_update_pmu_caps(struct pmu *pmu) +{ + if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) + update_pmu_cap_from_perfmonext(pmu); =20 - if (!intel_pmu_broken_perf_cap()) { - /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration = */ - rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities); + if (is_hybrid() && this_cpu_has(X86_FEATURE_PDCM)) { + rdmsrq(MSR_IA32_PERF_CAPABILITIES, + hybrid(pmu, intel_cap).capabilities); + + /* + * Restore perf_metrics on platforms with broken + * perf_capablities. + */ + if (intel_pmu_broken_perf_cap() && + hybrid_pmu(pmu)->pmu_type =3D=3D hybrid_big) + hybrid(pmu, intel_cap).perf_metrics =3D 1; } } =20 @@ -6329,9 +6349,7 @@ static bool init_hybrid_pmu(int cpu) if (!cpumask_empty(&pmu->supported_cpus)) goto end; =20 - if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) - update_pmu_cap(&pmu->pmu); - + intel_update_pmu_caps(&pmu->pmu); intel_pmu_check_hybrid_pmus(pmu); =20 if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask)) { @@ -8828,8 +8846,8 @@ __init int intel_pmu_init(void) * from the leaf 0xa. The core specific update will be done later * when a new type is online. */ - if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) - update_pmu_cap(NULL); + if (!is_hybrid()) + intel_update_pmu_caps(NULL); =20 if (x86_pmu.arch_pebs) { static_call_update(intel_pmu_disable_event_ext,