From nobody Tue Sep 29 04:43:15 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E17D53E5585; Wed, 12 Aug 2026 14:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786543885; cv=none; b=bzj06d31ba9+JlFzG1EgAHM6JxzaWZDGcSAATFpQ1n4ZI5ZCoqpkgyY83vSq8/ZThVcxhXaIFLBgph/elNyBaSSs+hckdkW0CtC03EVulRKGe64Ii3Obh0N2XtbNANAEDxm6Xg79oVfrMYONx9fU+Z/57YCNCQqgyzzeR/mUf3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786543885; c=relaxed/simple; bh=2NPsNAQKFbO2P8UhwiyvVdQzboBOqXYv6XCA3EGDRzg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=i3m5MbPhje93oe3H3nRbRHQujSRNqFOg0Hw/ONgkeqoIz5T69x2hACQvMGsvxqNNa+C02+hPb1UHajnFuCh+4s10esL0gMbdMAJns9nhpJVh4rdNyatTv2N3zNOn2smYcfmG/J6ag3uwqvQ/n+uVoH4HgZihZ6x9Xmr6cjQLxh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=S7Plfs18; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=r7HP28O+; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="S7Plfs18"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="r7HP28O+" Date: Wed, 12 Aug 2026 14:11:20 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1786543882; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yxMXwawI+EvYy27eXqoJYSPvq33tqKnef0jZRS47h3Y=; b=S7Plfs1869lyJ6q9JFWRP4cY3SF+qVmkFI450RmExLzQvNEHETID8zvjpwC2fxx/dXxwGx wk1CpCq7IvWG+f6n+CoKdvbBjZXRx3QYQF0bw/ZqOsQV+f0FtOBTXG3SZ6QVjwFhWWRobe gseSBatSxPzeuUxgD+a10RjDxV3VhUq+hrkD1ho4TubFxKnkEU4KMgcmkn19aQHYrIIY+M V/UsCtEG6LzMw/dgrKe01AL0PURN0WGGRv4kS5Wzc1CH9gINJ1yo0+sya7sjyCpB+yd9ov HdHdIW0iPz5cWKzD9bdP2oZdaqpKXTxAoEx0s2DVgXBwUQLj3LpudZOSvV6pIg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1786543882; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yxMXwawI+EvYy27eXqoJYSPvq33tqKnef0jZRS47h3Y=; b=r7HP28O+rNDZB8CklL2HcoKdwZbFG6Vcd7ILOr2LQNVSH9w5aGPVthTKpqOJzNfy/1o3sD WeQJKxzxgIMXfAAg== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86: Optimize ACR handling in match_prev_assignment() Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , Thomas Falcon , Zide Chen , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260717080342.1879573-8-dapeng1.mi@linux.intel.com> References: <20260717080342.1879573-8-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178654388005.442315.6803462420914116523.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 917d558b151cad5b05991e5eaee22efab33525ca Gitweb: https://git.kernel.org/tip/917d558b151cad5b05991e5eaee22efab= 33525ca Author: Dapeng Mi AuthorDate: Fri, 17 Jul 2026 16:03:41 +08:00 Committer: Peter Zijlstra CommitterDate: Mon, 10 Aug 2026 15:05:48 +02:00 perf/x86: Optimize ACR handling in match_prev_assignment() match_prev_assignment() currently forces a mismatch for ACR events, so ACR counter indices are reprogrammed on every scheduling pass. That causes avoidable overhead because disable and enable paths must touch multiple MSRs. The previous ACR assignment is already cached in acr_cfg_b[]. Use that state to compare the newly computed ACR counter indices in hwc->config1 against the cached value in acr_cfg_b[hwc->idx]. If they match, skip unnecessary disable and enable work. Also tighten is_acr_self_reload_event() so it first verifies the event is an ACR event before testing for the self-reload case. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Thomas Falcon Reviewed-by: Zide Chen Link: https://patch.msgid.link/20260717080342.1879573-8-dapeng1.mi@linux.in= tel.com --- arch/x86/events/core.c | 13 ++++++++++++- arch/x86/events/perf_event.h | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 143a6e7..8b3ea0a 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1297,6 +1297,17 @@ int x86_perf_rdpmc_index(struct perf_event *event) return event->hw.event_base_rdpmc; } =20 +static inline bool acr_match_prev_indices(struct perf_event *event, + struct cpu_hw_events *cpuc) +{ + struct hw_perf_event *hwc =3D &event->hw; + + if (!is_acr_event_group(event)) + return true; + /* ACR counter indices don't change. */ + return hwc->config1 =3D=3D cpuc->acr_cfg_b[hwc->idx]; +} + static inline int match_prev_assignment(struct perf_event *event, struct cpu_hw_events *cpuc, int i) @@ -1306,7 +1317,7 @@ static inline int match_prev_assignment(struct perf_e= vent *event, return hwc->idx =3D=3D cpuc->assign[i] && hwc->last_cpu =3D=3D smp_processor_id() && hwc->last_tag =3D=3D cpuc->tags[i] && - !is_acr_event_group(event); + acr_match_prev_indices(event, cpuc); } =20 static void x86_pmu_start(struct perf_event *event, int flags); diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index cc9cfaa..fa38111 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -141,7 +141,7 @@ static inline bool is_acr_self_reload_event(struct perf= _event *event) { struct hw_perf_event *hwc =3D &event->hw; =20 - if (hwc->idx < 0) + if (hwc->idx < 0 || !is_acr_event_group(event)) return false; =20 return test_bit(hwc->idx, (unsigned long *)&hwc->config1);