From nobody Tue Sep 29 10:32:55 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0FB838644D; Sat, 8 Aug 2026 20:48:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786222118; cv=none; b=MCv/ONgG35QNlRSiK9ZMifv3UXUz22esxxsEbL7NlQu0s76fqWBSRDU9+y1/xV9Ng7NbzJVDXM6K6JSlz9CCc4UsLSHiSLEXrihBlbC/uUS/D5XCEm8pkR5k20lWjjnrcGTjOjtftkHPt2zIXjKTCeOiwAcL8vCHO4Ei4L825a4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786222118; c=relaxed/simple; bh=H8AL/iy5Qt8g6MoCDyib3JP7J6T6n2sxZuLGo24JG+4=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=dvmfUBjgq33PZTk09dX86cc3ivbsyi8MfOfI6OgvJB6z82Xbw2XHzArgWgBFTdGEyNwB7XmhEteeHzrK2Q5/I5k2SthQdmBWctB11I7EvYaXNweWHwalrkJUEShhn7kvtl9h1etDJblgY3f1cPOaPmfSUZ/YDGUN2uhmuzvZXCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=S4YcLJfU; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VB6M+SP7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="S4YcLJfU"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VB6M+SP7" Date: Sat, 08 Aug 2026 20:48:33 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1786222114; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NV+wJKVgI8/q0Zt4dRfr3Xn6Jq7wufxjCTtnBl6GBN4=; b=S4YcLJfUmI+ahWbcf/HQ2XAGwApJlDcdjWVnwy337ZRTJJpn5S3eHbll2IvvC2a5/9fPAo FIfviy/sKBtyDToFmDaCG/341IgmyT+uDjFJl/wjPprTKPm8kR0G1IwRD9RkP1/rLy39Dl BMqxAW/ddRp0qe8yCOBeauoE2DoDwVqR9ElNWIojdGGfO4UZ1JQ/eBopOOdfOoLRzyc78i zAwvGrydChL8mzF7UU+T9481JHrmZihf2mpFoi/J0WllzgLEEq3tFA8E9pnkFG5YraZRAW tKplnqLiTgCDBYPErYnq2NMQa5VuKCYAT21b5d0+9r/wrbZaqaKDje2w5Y2PYg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1786222114; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NV+wJKVgI8/q0Zt4dRfr3Xn6Jq7wufxjCTtnBl6GBN4=; b=VB6M+SP73OaiKYX8JDZJcDF6pmq3wvVIP0nsUJ5YnthXeAoeCkHMhppdaKtcpST7yIXhaH UzAx1sEUVnumCKAA== From: "tip-bot2 for Boqun Feng" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] preempt: Introduce __preempt_count_{sub,add}_return() Cc: Boqun Feng , "Peter Zijlstra (Intel)" , Heiko Carstens , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260804161447.84806-4-boqun@kernel.org> References: <20260804161447.84806-4-boqun@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178622211346.442315.13862804947907471494.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: 4ad87eee546ef97e3a5ad80414327f41f48a4e70 Gitweb: https://git.kernel.org/tip/4ad87eee546ef97e3a5ad80414327f41f= 48a4e70 Author: Boqun Feng AuthorDate: Tue, 04 Aug 2026 09:14:25 -07:00 Committer: Peter Zijlstra CommitterDate: Sat, 08 Aug 2026 22:44:06 +02:00 preempt: Introduce __preempt_count_{sub,add}_return() In order to use preempt_count() to track the interrupt disable nesting level, __preempt_count_{add,sub}_return() are introduced, as their names suggest, these primitives return the new value of the preempt_count() after changing it. The following example shows the usage of it in local_interrupt_disable(): // increase the HARDIRQ_DISABLE bit new_count =3D __preempt_count_add_return(HARDIRQ_DISABLE_OFFSET); // if it's the first-time increment, then disable the interrupt // at hardware level. if ((new_count & HARDIRQ_DISABLE_MASK) =3D=3D HARDIRQ_DISABLE_OFFSET) { local_irq_save(flags); raw_cpu_write(local_interrupt_disable_state, flags); } Having these primitives will avoid a read of preempt_count() after changing preempt_count() on certain architectures. Signed-off-by: Boqun Feng Signed-off-by: Peter Zijlstra (Intel) Acked-by: Heiko Carstens # s390 Link: https://patch.msgid.link/20260804161447.84806-4-boqun@kernel.org --- arch/arm64/include/asm/preempt.h | 20 ++++++++++++++++++++ arch/s390/include/asm/preempt.h | 10 ++++++++++ arch/x86/include/asm/preempt.h | 10 ++++++++++ include/asm-generic/preempt.h | 14 ++++++++++++++ 4 files changed, 54 insertions(+) diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/pree= mpt.h index 932ea4b..9ecc276 100644 --- a/arch/arm64/include/asm/preempt.h +++ b/arch/arm64/include/asm/preempt.h @@ -55,6 +55,26 @@ static inline void __preempt_count_sub(int val) WRITE_ONCE(current_thread_info()->preempt.count, pc); } =20 +static inline int __preempt_count_add_return(int val) +{ + u32 pc =3D READ_ONCE(current_thread_info()->preempt.count); + + pc +=3D val; + WRITE_ONCE(current_thread_info()->preempt.count, pc); + + return pc; +} + +static inline int __preempt_count_sub_return(int val) +{ + u32 pc =3D READ_ONCE(current_thread_info()->preempt.count); + + pc -=3D val; + WRITE_ONCE(current_thread_info()->preempt.count, pc); + + return pc; +} + static inline bool __preempt_count_dec_and_test(void) { struct thread_info *ti =3D current_thread_info(); diff --git a/arch/s390/include/asm/preempt.h b/arch/s390/include/asm/preemp= t.h index 6e5821b..0a25d46 100644 --- a/arch/s390/include/asm/preempt.h +++ b/arch/s390/include/asm/preempt.h @@ -139,6 +139,16 @@ static __always_inline bool should_resched(int preempt= _offset) return unlikely(READ_ONCE(get_lowcore()->preempt_count) =3D=3D preempt_of= fset); } =20 +static __always_inline int __preempt_count_add_return(int val) +{ + return val + __atomic_add(val, &get_lowcore()->preempt_count); +} + +static __always_inline int __preempt_count_sub_return(int val) +{ + return __preempt_count_add_return(-val); +} + #define init_task_preempt_count(p) do { } while (0) /* Deferred to CPU bringup time */ #define init_idle_preempt_count(p, cpu) do { } while (0) diff --git a/arch/x86/include/asm/preempt.h b/arch/x86/include/asm/preempt.h index 578441d..1220656 100644 --- a/arch/x86/include/asm/preempt.h +++ b/arch/x86/include/asm/preempt.h @@ -85,6 +85,16 @@ static __always_inline void __preempt_count_sub(int val) raw_cpu_add_4(__preempt_count, -val); } =20 +static __always_inline int __preempt_count_add_return(int val) +{ + return raw_cpu_add_return_4(__preempt_count, val); +} + +static __always_inline int __preempt_count_sub_return(int val) +{ + return raw_cpu_add_return_4(__preempt_count, -val); +} + /* * Because we keep PREEMPT_NEED_RESCHED set when we do _not_ need to resch= edule * a decrement which hits zero means we have no preempt_count and should diff --git a/include/asm-generic/preempt.h b/include/asm-generic/preempt.h index 51f8f38..c8683c0 100644 --- a/include/asm-generic/preempt.h +++ b/include/asm-generic/preempt.h @@ -59,6 +59,20 @@ static __always_inline void __preempt_count_sub(int val) *preempt_count_ptr() -=3D val; } =20 +static __always_inline int __preempt_count_add_return(int val) +{ + *preempt_count_ptr() +=3D val; + + return *preempt_count_ptr(); +} + +static __always_inline int __preempt_count_sub_return(int val) +{ + *preempt_count_ptr() -=3D val; + + return *preempt_count_ptr(); +} + static __always_inline bool __preempt_count_dec_and_test(void) { /*