From nobody Tue Sep 29 10:32:56 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CC2C3290C7; Sat, 8 Aug 2026 20:48:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786222112; cv=none; b=GghtNh+HGuONFOYYnuWu54/hPeGy0ZfwFO4bvqtvEM95NAxJ4fhFd2CxkBBRR5O/OPzmo8sATM6RqYac+Z5OoVTd0k4wvocxXV5zk5xkwjsolePi0soViGGrrs/BahPPZDaDWOizjth9IzomAwnfbHb+5OfE5uKjsuTRwu1AV80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786222112; c=relaxed/simple; bh=gYh66G6038y/t8ArxRhxNLxxoD8cOfONTzQ9625Z2j0=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=fTCAHbT30dcYcMoCCIplPcw5NsIU3q060zzJ9RBG+Zfq9ssmygSFLqlBKe9hsPtm3pglTGKc0n3SYHVVBbVhKXd7BS/QEHORyojEjCBQlehZuQF0De0oOfAQ8SfaIkphwCsFf3XhLFtqL6p1ZP8YltKWJgJClF1DovLO2F/L7Ok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MbsCcNzZ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=h3Jcab2A; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MbsCcNzZ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="h3Jcab2A" Date: Sat, 08 Aug 2026 20:48:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1786222104; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zigR/qAro8T287Wm4axZgpzc+O3OpZNemI+eKLNXGk0=; b=MbsCcNzZT6JiHK1mJjxt6eSUX4g28ifOmnorVcqFb7L/kOhvq6dBk07UZ2iMyniV6UWdhD 0V2BraLCny98kTKheML5rub0W0PZELCJLKQPdeiuNZ+mH/l8NDo0BW968JLnCZiqyu9x6x hP982HunDUGerpB3C1/K3PWiq9+NW0VnpOWkco5ji8ExnkW3Zza0q3gaFgtL3HGQ9q73UV b6a5TCEkubdJqh/+syedL7kqhCQUVO9WsKytdNMkG5HFvyG6dLKFTikp23+aj/3O3gerxk ZUv1wcVtj2Z/pKtSP5C/Je/ML8gm1Hqhcv8mN+c1LQVg4YtB9laLkXZ4D60jzg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1786222104; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zigR/qAro8T287Wm4axZgpzc+O3OpZNemI+eKLNXGk0=; b=h3Jcab2AR0lBUlYaB6UOSW68IgHByxk2eTo7cifaklBLqM55MNNxIU534w0Qd9Q2l/ASGG DfZ3dyskwc0isJDg== From: "tip-bot2 for Boqun Feng" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] arm64: sched/preempt: Enable HAS_SEPARATE_PREEMPT_RESCHED_BITS Cc: Boqun Feng , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260804161447.84806-12-boqun@kernel.org> References: <20260804161447.84806-12-boqun@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178622210298.442315.16258034056736598907.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: c9bae17d96b93ce05ff2eeef08165c24c7f5e7e3 Gitweb: https://git.kernel.org/tip/c9bae17d96b93ce05ff2eeef08165c24c= 7f5e7e3 Author: Boqun Feng AuthorDate: Tue, 04 Aug 2026 09:14:33 -07:00 Committer: Peter Zijlstra CommitterDate: Sat, 08 Aug 2026 22:44:08 +02:00 arm64: sched/preempt: Enable HAS_SEPARATE_PREEMPT_RESCHED_BITS Arm64 already uses 64-bit preempt count and the need reschedule bit is maintained in a separate 32-bit word from the preempt count. Therefore preempt count has enough bits to represent 16 levels of NMI nesting, hence enable it for arm64. This saves a per-CPU variable and additional instructions in the NMI path. Signed-off-by: Boqun Feng Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260804161447.84806-12-boqun@kernel.org --- arch/arm64/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b3afe06..349c353 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -247,6 +247,7 @@ config ARM64 select PCI_SYSCALL if PCI select POWER_RESET select POWER_SUPPLY + select HAS_SEPARATE_PREEMPT_RESCHED_BITS select SPARSE_IRQ select SWIOTLB select SYSCTL_EXCEPTION_TRACE