From nobody Fri Jul 24 21:53:25 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84A37439320; Thu, 23 Jul 2026 10:32:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784802754; cv=none; b=XyjTBEmn4226XljIRrpXixEfmQ3Ee6r1MuTqAnuYXHqOXDSahj1UJj/pUVkh2k0DA9VB5FvgmWGLAKwfdk7A+QBdCG9Lsvoe3wLn8dQ9Nkya2g5LlhLlZ0VKvTWkrXNubIf0l0BkcF/FmWEbRC9nkOzzRciXJStDYA62EaYEuAQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784802754; c=relaxed/simple; bh=o+HqiQZGkbEghrasA5bj42GOWVWle6EabjkxtwjBHdU=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=XwJlBCgCIOTXe0RfsybqwF3X21S7P3s3qsfvIqlGWS+Mf2kb7C3LrWNj7VLUHpEx09V5NFZiEhoSU9tFSe+h6MAQTSRN9e+/xuO6LfQav2vM0FzH5z1OJYSpcyxVljmwff9HoekYXUyetPedf63HInmuAMkAckHK3EWIcCgPLYk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RzVp92Xg; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/JywZNbT; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RzVp92Xg"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/JywZNbT" Date: Thu, 23 Jul 2026 10:32:26 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784802747; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p+Etdclw5mO+vUxkNoi12mvoSum71PEUzHfVgp4Pmi8=; b=RzVp92Xgz5f/d4dBtOjYrpALjK9TKzXMyn9hrSY92QkjaNWk2fJ1v+Wjtp1HcnY/nA4yC+ gC1pgzUSLy1TVAryNkfuZhOlVwUcObOSyDA7KeRmoD9VJfN+Y365uVuimn6JBD/omCdDkj mdr0zAhTdA6Ij6j9KxXUMM84qJWNFwDnrM0ZCTonm3eczeXeLCgVgjALlsE/F9EwxyK9pJ F0rBzs2CUAtPU7ygA22xLXN69a2sPFg0+a9+zDUIeQ3xbvw5X+ol3kxebc7DjuHh47rfny 3sh6WVppQEba4KBoAxbIK33it2HwSSjC76cWJU1omi2JGvZs1E+WhbhDpTavIA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784802747; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p+Etdclw5mO+vUxkNoi12mvoSum71PEUzHfVgp4Pmi8=; b=/JywZNbTBNzXvPZfDfCjdI9kcdIz9Gqj5+JFJkkXAAuofjckxBSoNmHT14AG7Ht3WJBsNr 7o8NWj2ZdNOPTAAA== From: "tip-bot2 for Chuyi Zhou" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/mm] x86/mm: Cap flush_tlb_info alignment at 64 bytes Cc: Chuyi Zhou , Thomas Gleixner , Sebastian Andrzej Siewior , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260709122933.4021501-12-zhouchuyi@bytedance.com> References: <20260709122933.4021501-12-zhouchuyi@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178480274608.2943223.8446915086652524186.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/mm branch of tip: Commit-ID: c86f522bb57b257befe2ff5fbcb4b94065abb011 Gitweb: https://git.kernel.org/tip/c86f522bb57b257befe2ff5fbcb4b9406= 5abb011 Author: Chuyi Zhou AuthorDate: Thu, 09 Jul 2026 20:29:30 +08:00 Committer: Thomas Gleixner CommitterDate: Thu, 23 Jul 2026 12:30:31 +02:00 x86/mm: Cap flush_tlb_info alignment at 64 bytes A stack allocated flush_tlb_info should keep cacheline alignment to avoid the regression that motivated the per-CPU storage, but using SMP_CACHE_BYTES directly can make the stack frame grow excessively on configurations with large cache lines. This was addressed by commit 780e0106d468 ("x86/mm/tlb: Revert "x86/mm: Align TLB invalidation info""), where the stack consumption reached 320 bytes. Add FLUSH_TLB_INFO_ALIGN and cap the type alignment at 64 bytes. The existing per-CPU flush_tlb_info instance remains DEFINE_PER_CPU_SHARED_ALIGNED(), so its per-CPU shared-cacheline alignment is unchanged. This prepares for moving flush_tlb_info back to stack storage without reintroducing the old large-cacheline stack usage problem. Signed-off-by: Chuyi Zhou Signed-off-by: Thomas Gleixner Reviewed-by: Sebastian Andrzej Siewior Link: https://patch.msgid.link/20260709122933.4021501-12-zhouchuyi@bytedanc= e.com --- arch/x86/include/asm/tlbflush.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 0545fe7..70098d4 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -4,6 +4,7 @@ =20 #include #include +#include #include =20 #include @@ -212,6 +213,12 @@ extern u16 invlpgb_count_max; extern void initialize_tlbstate_and_flush(void); =20 /* + * Keep stack-allocated flush_tlb_info cacheline aligned, but cap the + * alignment to avoid excessive stack usage on large-cacheline systems. + */ +#define FLUSH_TLB_INFO_ALIGN MIN(SMP_CACHE_BYTES, 64) + +/* * TLB flushing: * * - flush_tlb_all() flushes all processes TLBs @@ -249,7 +256,7 @@ struct flush_tlb_info { u8 stride_shift; u8 freed_tables; u8 trim_cpumask; -}; +} __aligned(FLUSH_TLB_INFO_ALIGN); =20 void flush_tlb_local(void); void flush_tlb_one_user(unsigned long addr);