From nobody Sat Jul 25 01:53:24 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF1F12EA75E; Mon, 20 Jul 2026 19:27:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784575651; cv=none; b=VfcpY23ATlZddKWzzjir4XrVOYrGt9Dp6G5im2rb5WX3shpDTUmZNsEWuVApjTP2OFfLSdEnPljIOJMG/zHsOppdHC9ko9lGyGlqntAITyTpM3lBbRRzp2YIs/mQGH+CLkzwMeZBNp1vTWNxBxAixK46uYL7MSn+NP4+5DQWn/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784575651; c=relaxed/simple; bh=llivNVYIbgfcPzpP/FHcw0kdrkZZdqiq8OpJDyrY0Jo=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=cd/85j9LrTma4KuBSGFY7LqTfPI+/I9NcMhMQ+V9JBmLEC2iZzoh3e9rtPB1RpHa0JBcZAj2FJ+tG3zzaO1p5qAtQ08NYxvrqCH94CBUGfsLajZjWPUjKLqW0L8wwlh2Ywfm0cTwISov6IhohDy7mi70moAUJfXKj3EBFvs7E88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IH5FnCHJ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Ejw6eKKr; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IH5FnCHJ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Ejw6eKKr" Date: Mon, 20 Jul 2026 19:27:25 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784575647; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9MEGD2G3RyL2xSjVoV75bLWDo0lrcz8whAQs6LJcdq4=; b=IH5FnCHJbFZwy0mI8dI8nTsp7n6olnZRa7pV7JWc2xF2gGb5hnhwez7WTP4l0GcG1yC4kp 7nS5yKj4UOK1tPo6iAbyYYt4U5sjpwv+Jm4BVMQDFKwGHa9M7WIFfsD7yexANgAclwUVC5 4m+woNiL7CL52rVip7IloZMD6qsHZwIU/Ex2TpJENj31dXz7cZ7jNnLLwdbv4ohJp7bRHx CiEqVSCRqc3CR8fY9UPVR3qq95RGqzJvJbrxX84ceGnpM1aw/s617+XfZ4XAGtMGZ0kV1V C2E0OmV8fCy7h1ik3VoYTdQnaE4WIfnIVzlXD7Cx0LHcMTPL7i27bfn3wvIAmw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784575647; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9MEGD2G3RyL2xSjVoV75bLWDo0lrcz8whAQs6LJcdq4=; b=Ejw6eKKrl7EyrRqzmUSRrXL8ENVeKuxb2QHsB0mFjQaOjoy/dK4BKZFoZtEyI0pKyyWYKo jjuZbBZ9b5niKcDQ== From: "tip-bot2 for Melody Wang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cleanups] x86/apic: Ensure ICR register write value is handled as 32 bits Cc: Melody Wang , "Borislav Petkov (AMD)" , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260708012117.177959-1-huibo.wang@amd.com> References: <20260708012117.177959-1-huibo.wang@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178457564581.2943223.6712176186819181288.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cleanups branch of tip: Commit-ID: cdb4d57c3e497fe99a9ffa54f085b75130b12b5a Gitweb: https://git.kernel.org/tip/cdb4d57c3e497fe99a9ffa54f085b7513= 0b12b5a Author: Melody Wang AuthorDate: Wed, 08 Jul 2026 01:21:17=20 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 20 Jul 2026 11:58:50 -07:00 x86/apic: Ensure ICR register write value is handled as 32 bits The low 32-bit ICR data is prepared by __prepare_ICR(), which returns a 32-= bit value. However, when this value is assigned to a new variable, it's easy to mistakenly declare that variable with a different width. To avoid this class of mistakes, use __prepare_ICR() directly as the functi= on argument instead of storing its result in an intermediate variable. This al= so shaves off a bunch of lines in the code. There should be no functionality change resulting from this. Signed-off-by: Melody Wang Signed-off-by: Borislav Petkov (AMD) Acked-by: Thomas Gleixner Link: https://patch.msgid.link/20260708012117.177959-1-huibo.wang@amd.com --- arch/x86/kernel/apic/local.h | 4 +--- arch/x86/kernel/apic/x2apic_phys.c | 4 +--- arch/x86/kernel/apic/x2apic_savic.c | 5 +---- 3 files changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 998efd4..090dd71 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,9 +44,7 @@ static inline unsigned int __prepare_ICR(unsigned int sho= rtcut, int vector, #ifdef CONFIG_X86_X2APIC static inline void __x2apic_send_IPI_dest(unsigned int apicid, int vector,= unsigned int dest) { - unsigned long cfg =3D __prepare_ICR(0, vector, dest); - - native_x2apic_icr_write(cfg, apicid); + native_x2apic_icr_write(__prepare_ICR(0, vector, dest), apicid); } #endif =20 diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2ap= ic_phys.c index 10f7902..090647c 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -85,11 +85,9 @@ static void =20 static void __x2apic_send_IPI_shorthand(int vector, u32 which) { - unsigned long cfg =3D __prepare_ICR(which, vector, 0); - /* x2apic MSRs are special and need a special fence: */ weak_wrmsr_fence(); - native_x2apic_icr_write(cfg, 0); + native_x2apic_icr_write(__prepare_ICR(which, vector, 0), 0); } =20 void x2apic_send_IPI_allbutself(int vector) diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2a= pic_savic.c index dbc5678..4bc6d7e 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -243,10 +243,7 @@ static void savic_write(u32 reg, u32 data) =20 static void send_ipi(u32 dest, unsigned int vector, unsigned int dsh) { - unsigned int icr_low; - - icr_low =3D __prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL); - savic_icr_write(icr_low, dest); + savic_icr_write(__prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL), dest); } =20 static void savic_send_ipi(int cpu, int vector)