From nobody Sat Jul 25 03:47:37 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38C101A9F97; Sun, 19 Jul 2026 09:44:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784454293; cv=none; b=GBZUKALAxVOMEIM0iK7fSwaYvY35JxxJmEPGlSJI1x844AJHjiNx50WO9gwRVVJ1X7HxCGtg9a7CbU0IzQcYBzSOb0094DRMaC7WW+YBwj7AyFoQiFHP90803K3uArM+msJjw7wPRY17UuheoANkXHkI+DXBYTw2hz7rRdtlR0M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784454293; c=relaxed/simple; bh=0y5V4DI7u1bdDlBg0fyQnSjo1aWEk2G2EkuQxlsafIs=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=XhHIHDR4F58jmzUm9ZbqEKiY8EnS7GYQ6sEUHMHVIyFwN4Wyl8r/vpFRKGQ7U1thbIbCcHWqZ97JVbQvnWbfJ6y9YMaIgRJr02PgdC0nWZ4v7ZDrWykS77tGtikP8zepKKE/H+qHRXHozrmyWSuzsz8iDOgEiE2Jqdl18hx0Ll8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Bw5WrU+l; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=YthDXfdm; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Bw5WrU+l"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="YthDXfdm" Date: Sun, 19 Jul 2026 09:44:48 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784454290; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HP/5RU7b3zfKuDskXKaqCb7eGfyFR9hGtJjkiAttm0U=; b=Bw5WrU+l96WnoN4jf+47hLxFQBzZc1tlEvBzEG93i2HEIQ+yQTfTgzIt2cd6wYJQRghUEt QWvVrSxgWu2jRmS/o2qHjnEwmTuF6/SqGLm23nuIKBdX5gS6l6SbOijCZxd7IbGrTVdl11 U7Il71Oha+lNfT/Iqdt4EPlKpEAx1plUeTWYGucsNOd3mjxatxoFvIavqMPnNzmyR39NpN 1iteUh8yzcs6bGBLC7T4DaxccA6yB5EU+VS1r/ymm86dltP6t19E4jdbB9VZMdu7faJjH4 x+YB30tbHFX9dxIGnSQFpFWtaazQbnoEODxqAbul1rSHxp1nmvUjr+KLGRWO7g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784454290; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HP/5RU7b3zfKuDskXKaqCb7eGfyFR9hGtJjkiAttm0U=; b=YthDXfdmEtLR9CTR1wtVBgt+Lg24oGrJ4lXjc/TN/5e1A3FGtwkXHC8p1GeYBoL+xgTEZ/ K41MIcGlg1HgtrBw== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/msr] x86/mce: Work around build warning after MSR-interface switch Cc: kernel test robot , Juergen Gross , Ingo Molnar , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260703105555.1758819-1-jgross@suse.com> References: <20260703105555.1758819-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178445428820.2943223.2475446099844170100.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/msr branch of tip: Commit-ID: a7187ca1e72505fd6785b0ce537ae066773a5532 Gitweb: https://git.kernel.org/tip/a7187ca1e72505fd6785b0ce537ae0667= 73a5532 Author: Juergen Gross AuthorDate: Fri, 03 Jul 2026 12:55:55 +02:00 Committer: Ingo Molnar CommitterDate: Sun, 19 Jul 2026 11:39:18 +02:00 x86/mce: Work around build warning after MSR-interface switch The recent switch to 64-bit MSR interfaces introduced a build warning. Work it around with a __maybe_unused annotation. After the full conversion of the APIs we'll be able to address this more robustly by making sure the APIs consume all the values as far the compiler is concerned, so that the compiler doesn't emit such nuisance warnings. [ mingo: Updated the changelog. ] Fixes: cff219368bd0 ("x86/mce: Stop using 32-bit MSR interfaces") Closes: https://lore.kernel.org/oe-kbuild-all/202607031726.ZOwu4snu-lkp@int= el.com/ Reported-by: kernel test robot Signed-off-by: Juergen Gross Signed-off-by: Ingo Molnar Link: https://patch.msgid.link/20260703105555.1758819-1-jgross@suse.com --- arch/x86/kernel/cpu/mce/p5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c index eb99f38..3c2b6cc 100644 --- a/arch/x86/kernel/cpu/mce/p5.c +++ b/arch/x86/kernel/cpu/mce/p5.c @@ -44,7 +44,7 @@ noinstr void pentium_machine_check(struct pt_regs *regs) /* Set up machine check reporting for processors with Intel style MCE: */ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { - u64 q; + u64 __maybe_unused q; =20 /* Default P5 to off as its often misconnected: */ if (!mce_p5_enabled)