From nobody Sat Jul 25 05:31:26 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7015B3B71D3; Fri, 17 Jul 2026 09:42:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784281364; cv=none; b=RPRYnGylQ0NOjyiTPSpXhf+ixbwQnW+QKI6iYZ856lWmePW/hMN49pPHVTmCMj1oCXgA4VEIvf530sPtBly29TlAnvBj1/g36MzHpZSheP1v5/itmDp9IeUBbGtqdpG5BeYzGGcPw7BuD7uB0Dy3cgavMqCU3aOP/x8w+ZLOugs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784281364; c=relaxed/simple; bh=szmyazSkUtL7To395LZ8pQswWNQL8tXNQXAwLccEuUs=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=goNgKTyVA3xQr0fuo07i11EYEOPhvyzwL2I/7JU7aS2JYqmgKhVNcgeEdLTCct3T9WLsNZjpvG/yBGTKQvbx24GNnVuvUUQJtohJGIu8tc9hhuiCOpJBQjst5RBY13PT1bWs99gL/CCqXvX0aa4a+gRlNI0Vvonh0chs0FDXIr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=AbyvMKLo; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RwjSXzpy; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="AbyvMKLo"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RwjSXzpy" Date: Fri, 17 Jul 2026 09:42:38 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784281359; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VdUsX9qjEIi/yc3dzT5GrL65fUr2AECW9j/iSIs7GGs=; b=AbyvMKLokZ7mEyEZDkLonKFMJUYZWAgJe4htLOJ4GjNyQ9A6CU8c3gKCx5BAuYfcdcTzF1 p2F4O+UPeqCOU1lnLk+Qw7DpgT7rngEtYdRI/lExVSexGy5tjdhKgeK0Yjg7OJ0db6DqVM huqFRS88hRsNYovIOj23uI/jRLQf/Sgw9f/LKKiPzFlOHvFoPPsip+xWNX9RS2s26sOc0n BWS4JV8oM7jqUSWbZe2cj/7mkQrGb9EurqSrxUQSJ8eXb71G4rQSxNah/sISRtSG/NmGne myZtVwHRPoSMhT8YFvV0KRvZUu6fjp5eklc1blQMsDJ8UaW6Wu8udV4j7mVPxw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784281359; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VdUsX9qjEIi/yc3dzT5GrL65fUr2AECW9j/iSIs7GGs=; b=RwjSXzpyv6XkpFkMDChMGauOD4E3Mc67kcF4/s8lg6TeHjTUJjiqxsxy0Hwug1v+dXh639 OO6qtiOiY8CPY2Bw== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/msr] x86/mtrr: Stop using 32-bit MSR interfaces Cc: Juergen Gross , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260703112344.1762985-1-jgross@suse.com> References: <20260703112344.1762985-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178428135806.1844600.15250132067576645935.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/msr branch of tip: Commit-ID: a415e3520545e2a83f9c22a45d5cbebb1b64e1f0 Gitweb: https://git.kernel.org/tip/a415e3520545e2a83f9c22a45d5cbebb1= b64e1f0 Author: Juergen Gross AuthorDate: Fri, 03 Jul 2026 13:23:44 +02:00 Committer: Ingo Molnar CommitterDate: Fri, 17 Jul 2026 11:25:49 +02:00 x86/mtrr: Stop using 32-bit MSR interfaces The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and wrmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross Signed-off-by: Ingo Molnar Cc: H. Peter Anvin Link: https://patch.msgid.link/20260703112344.1762985-1-jgross@suse.com --- arch/x86/kernel/cpu/mtrr/amd.c | 31 +++++---- arch/x86/kernel/cpu/mtrr/centaur.c | 18 ++--- arch/x86/kernel/cpu/mtrr/cleanup.c | 18 ++--- arch/x86/kernel/cpu/mtrr/generic.c | 97 +++++++++++++++-------------- arch/x86/kernel/cpu/mtrr/mtrr.c | 4 +- 5 files changed, 92 insertions(+), 76 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c index ef3e8e4..a73715d 100644 --- a/arch/x86/kernel/cpu/mtrr/amd.c +++ b/arch/x86/kernel/cpu/mtrr/amd.c @@ -10,20 +10,23 @@ static void amd_get_mtrr(unsigned int reg, unsigned long *base, unsigned long *size, mtrr_type *type) { - unsigned long low, high; + unsigned long val; + struct msr msr; =20 - rdmsr(MSR_K6_UWCCR, low, high); + rdmsrq(MSR_K6_UWCCR, msr.q); /* Upper dword is region 1, lower is region 0 */ if (reg =3D=3D 1) - low =3D high; + val =3D msr.h; + else + val =3D msr.l; /* The base masks off on the right alignment */ - *base =3D (low & 0xFFFE0000) >> PAGE_SHIFT; + *base =3D (val & 0xFFFE0000) >> PAGE_SHIFT; *type =3D 0; - if (low & 1) + if (val & 1) *type =3D MTRR_TYPE_UNCACHABLE; - if (low & 2) + if (val & 2) *type =3D MTRR_TYPE_WRCOMB; - if (!(low & 3)) { + if (!(val & 3)) { *size =3D 0; return; } @@ -42,8 +45,8 @@ amd_get_mtrr(unsigned int reg, unsigned long *base, * +1 000 0000 0000 0100 * *128K ... */ - low =3D (~low) & 0x1FFFC; - *size =3D (low + 4) << (15 - PAGE_SHIFT); + val =3D (~val) & 0x1FFFC; + *size =3D (val + 4) << (15 - PAGE_SHIFT); } =20 /** @@ -59,12 +62,16 @@ amd_get_mtrr(unsigned int reg, unsigned long *base, static void amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtr= r_type type) { + struct msr msr; u32 regs[2]; =20 /* * Low is MTRR0, High MTRR 1 */ - rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); + rdmsrq(MSR_K6_UWCCR, msr.q); + regs[0] =3D msr.l; + regs[1] =3D msr.h; + /* * Blank to disable */ @@ -89,7 +96,9 @@ amd_set_mtrr(unsigned int reg, unsigned long base, unsign= ed long size, mtrr_type * disable local interrupts, write back the cache, set the mtrr */ wbinvd(); - wrmsr(MSR_K6_UWCCR, regs[0], regs[1]); + msr.l =3D regs[0]; + msr.h =3D regs[1]; + wrmsrq(MSR_K6_UWCCR, msr.q); } =20 static int diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/= centaur.c index 6f6c3ae..e32cca1 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -65,26 +65,26 @@ static void centaur_set_mcr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) { - unsigned long low, high; + struct msr val; =20 if (size =3D=3D 0) { /* Disable */ - high =3D low =3D 0; + val.q =3D 0; } else { - high =3D base << PAGE_SHIFT; + val.h =3D base << PAGE_SHIFT; if (centaur_mcr_type =3D=3D 0) { /* Only support write-combining... */ - low =3D -size << PAGE_SHIFT | 0x1f; + val.l =3D -size << PAGE_SHIFT | 0x1f; } else { if (type =3D=3D MTRR_TYPE_UNCACHABLE) - low =3D -size << PAGE_SHIFT | 0x02; /* NC */ + val.l =3D -size << PAGE_SHIFT | 0x02; /* NC */ else - low =3D -size << PAGE_SHIFT | 0x09; /* WWO, WC */ + val.l =3D -size << PAGE_SHIFT | 0x09; /* WWO, WC */ } } - centaur_mcr[reg].high =3D high; - centaur_mcr[reg].low =3D low; - wrmsr(MSR_IDT_MCR0 + reg, low, high); + centaur_mcr[reg].high =3D val.h; + centaur_mcr[reg].low =3D val.l; + wrmsrq(MSR_IDT_MCR0 + reg, val.q); } =20 static int diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/= cleanup.c index e3eee9a..cd1a6de 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -658,8 +658,8 @@ static int __init mtrr_search_optimal_index(void) int __init mtrr_cleanup(void) { unsigned long x_remove_base, x_remove_size; - unsigned long base, size, def, dummy; - u64 chunk_size, gran_size; + u64 def, chunk_size, gran_size; + unsigned long base, size; mtrr_type type; int index_good; int i; @@ -670,7 +670,7 @@ int __init mtrr_cleanup(void) if (!cpu_feature_enabled(X86_FEATURE_MTRR) || enable_mtrr_cleanup < 1) return 0; =20 - rdmsr(MSR_MTRRdefType, def, dummy); + rdmsrq(MSR_MTRRdefType, def); def &=3D 0xff; if (def !=3D MTRR_TYPE_UNCACHABLE) return 0; @@ -806,7 +806,7 @@ early_param("disable_mtrr_trim", disable_mtrr_trim_setu= p); =20 int __init amd_special_default_mtrr(void) { - u32 l, h; + u64 q; =20 if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) @@ -814,13 +814,13 @@ int __init amd_special_default_mtrr(void) if (boot_cpu_data.x86 < 0xf) return 0; /* In case some hypervisor doesn't pass SYSCFG through: */ - if (rdmsr_safe(MSR_AMD64_SYSCFG, &l, &h) < 0) + if (rdmsrq_safe(MSR_AMD64_SYSCFG, &q) < 0) return 0; /* * Memory between 4GB and top of mem is forced WB by this magic bit. * Reserved before K8RevF, but should be zero there. */ - if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) =3D=3D + if ((q & (Tom2Enabled | Tom2ForceMemTypeWB)) =3D=3D (Tom2Enabled | Tom2ForceMemTypeWB)) return 1; return 0; @@ -854,9 +854,9 @@ real_trim_memory(unsigned long start_pfn, unsigned long= limit_pfn) */ int __init mtrr_trim_uncached_memory(unsigned long end_pfn) { - unsigned long i, base, size, highest_pfn =3D 0, def, dummy; + unsigned long i, base, size, highest_pfn =3D 0; mtrr_type type; - u64 total_trim_size; + u64 def, total_trim_size; /* extra one for all 0 */ int num[MTRR_NUM_TYPES + 1]; =20 @@ -870,7 +870,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_= pfn) if (!cpu_feature_enabled(X86_FEATURE_MTRR) || disable_mtrr_trim) return 0; =20 - rdmsr(MSR_MTRRdefType, def, dummy); + rdmsrq(MSR_MTRRdefType, def); def &=3D MTRR_DEF_TYPE_TYPE; if (def !=3D MTRR_TYPE_UNCACHABLE) return 0; diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 3a83170..67cf69f 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -103,7 +103,7 @@ u32 phys_hi_rsvd; */ static inline void k8_check_syscfg_dram_mod_en(void) { - u32 lo, hi; + struct msr val; =20 if (!((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) && (boot_cpu_data.x86 >=3D 0x0f))) @@ -112,13 +112,13 @@ static inline void k8_check_syscfg_dram_mod_en(void) if (cc_platform_has(CC_ATTR_HOST_SEV_SNP)) return; =20 - rdmsr(MSR_AMD64_SYSCFG, lo, hi); - if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { + rdmsrq(MSR_AMD64_SYSCFG, val.q); + if (val.l & K8_MTRRFIXRANGE_DRAM_MODIFY) { pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" " not cleared by BIOS, clearing this bit\n", smp_processor_id()); - lo &=3D ~K8_MTRRFIXRANGE_DRAM_MODIFY; - mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi); + val.l &=3D ~K8_MTRRFIXRANGE_DRAM_MODIFY; + mtrr_wrmsr(MSR_AMD64_SYSCFG, val.l, val.h); } } =20 @@ -557,8 +557,14 @@ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) static void get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) { - rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); - rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); + struct msr val; + + rdmsrq(MTRRphysBase_MSR(index), val.q); + vr->base_lo =3D val.l; + vr->base_hi =3D val.h; + rdmsrq(MTRRphysMask_MSR(index), val.q); + vr->mask_lo =3D val.l; + vr->mask_hi =3D val.h; } =20 /* Fill the MSR pair relating to a var range */ @@ -577,17 +583,17 @@ void fill_mtrr_var_range(unsigned int index, =20 static void get_fixed_ranges(mtrr_type *frs) { - unsigned int *p =3D (unsigned int *)frs; + u64 *p =3D (u64 *)frs; int i; =20 k8_check_syscfg_dram_mod_en(); =20 - rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); + rdmsrq(MSR_MTRRfix64K_00000, p[0]); =20 for (i =3D 0; i < 2; i++) - rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); + rdmsrq(MSR_MTRRfix16K_80000 + i, p[1 + i]); for (i =3D 0; i < 8; i++) - rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); + rdmsrq(MSR_MTRRfix4K_C0000 + i, p[3 + i]); } =20 void mtrr_save_fixed_ranges(void *info) @@ -689,31 +695,26 @@ static void __init print_mtrr_state(void) bool __init get_mtrr_state(void) { struct mtrr_var_range *vrs; - unsigned lo, dummy; unsigned int i; + u64 q; =20 vrs =3D mtrr_state.var_ranges; =20 - rdmsr(MSR_MTRRcap, lo, dummy); - mtrr_state.have_fixed =3D lo & MTRR_CAP_FIX; + rdmsrq(MSR_MTRRcap, q); + mtrr_state.have_fixed =3D q & MTRR_CAP_FIX; =20 for (i =3D 0; i < num_var_ranges; i++) get_mtrr_var_range(i, &vrs[i]); if (mtrr_state.have_fixed) get_fixed_ranges(mtrr_state.fixed_ranges); =20 - rdmsr(MSR_MTRRdefType, lo, dummy); - mtrr_state.def_type =3D lo & MTRR_DEF_TYPE_TYPE; - mtrr_state.enabled =3D (lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT; + rdmsrq(MSR_MTRRdefType, q); + mtrr_state.def_type =3D q & MTRR_DEF_TYPE_TYPE; + mtrr_state.enabled =3D (q & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT; =20 if (amd_special_default_mtrr()) { - unsigned low, high; - /* TOP_MEM2 */ - rdmsr(MSR_K8_TOP_MEM2, low, high); - mtrr_tom2 =3D high; - mtrr_tom2 <<=3D 32; - mtrr_tom2 |=3D low; + rdmsrq(MSR_K8_TOP_MEM2, mtrr_tom2); mtrr_tom2 &=3D 0xffffff800000ULL; } =20 @@ -750,7 +751,9 @@ void __init mtrr_state_warn(void) */ void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) { - if (wrmsr_safe(msr, a, b) < 0) { + struct msr val =3D { .l =3D a, .h =3D b }; + + if (wrmsrq_safe(msr, val.q) < 0) { pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", smp_processor_id(), msr, a, b); } @@ -765,11 +768,11 @@ void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) */ static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) { - unsigned lo, hi; + struct msr val; =20 - rdmsr(msr, lo, hi); + rdmsrq(msr, val.q); =20 - if (lo !=3D msrwords[0] || hi !=3D msrwords[1]) { + if (val.l !=3D msrwords[0] || val.h !=3D msrwords[1]) { mtrr_wrmsr(msr, msrwords[0], msrwords[1]); *changed =3D true; } @@ -806,9 +809,8 @@ generic_get_free_region(unsigned long base, unsigned lo= ng size, int replace_reg) static void generic_get_mtrr(unsigned int reg, unsigned long *base, unsigned long *size, mtrr_type *type) { - u32 mask_lo, mask_hi, base_lo, base_hi; + u64 tmp, mask, base_msr; unsigned int hi; - u64 tmp, mask; =20 /* * get_mtrr doesn't need to update mtrr_state, also it could be called @@ -816,9 +818,9 @@ static void generic_get_mtrr(unsigned int reg, unsigned= long *base, */ get_cpu(); =20 - rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); + rdmsrq(MTRRphysMask_MSR(reg), mask); =20 - if (!(mask_lo & MTRR_PHYSMASK_V)) { + if (!(mask & MTRR_PHYSMASK_V)) { /* Invalid (i.e. free) range */ *base =3D 0; *size =3D 0; @@ -826,10 +828,10 @@ static void generic_get_mtrr(unsigned int reg, unsign= ed long *base, goto out_put_cpu; } =20 - rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); + rdmsrq(MTRRphysBase_MSR(reg), base_msr); =20 /* Work out the shifted address mask: */ - tmp =3D (u64)mask_hi << 32 | (mask_lo & PAGE_MASK); + tmp =3D mask & PAGE_MASK; mask =3D (u64)phys_hi_rsvd << 32 | tmp; =20 /* Expand tmp with high bits to all 1s: */ @@ -849,8 +851,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned= long *base, * contiguous range: */ *size =3D -mask >> PAGE_SHIFT; - *base =3D (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; - *type =3D base_lo & MTRR_PHYSBASE_TYPE; + *base =3D base_msr >> PAGE_SHIFT; + *type =3D base_msr & MTRR_PHYSBASE_TYPE; =20 out_put_cpu: put_cpu(); @@ -884,21 +886,21 @@ static int set_fixed_ranges(mtrr_type *frs) */ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range = *vr) { - unsigned int lo, hi; bool changed =3D false; + struct msr val; =20 - rdmsr(MTRRphysBase_MSR(index), lo, hi); - if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) !=3D (lo & ~MTRR_PHYSBASE_RSVD) - || (vr->base_hi & ~phys_hi_rsvd) !=3D (hi & ~phys_hi_rsvd)) { + rdmsrq(MTRRphysBase_MSR(index), val.q); + if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) !=3D (val.l & ~MTRR_PHYSBASE_RSVD) + || (vr->base_hi & ~phys_hi_rsvd) !=3D (val.h & ~phys_hi_rsvd)) { =20 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); changed =3D true; } =20 - rdmsr(MTRRphysMask_MSR(index), lo, hi); + rdmsrq(MTRRphysMask_MSR(index), val.q); =20 - if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) !=3D (lo & ~MTRR_PHYSMASK_RSVD) - || (vr->mask_hi & ~phys_hi_rsvd) !=3D (hi & ~phys_hi_rsvd)) { + if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) !=3D (val.l & ~MTRR_PHYSMASK_RSVD) + || (vr->mask_hi & ~phys_hi_rsvd) !=3D (val.h & ~phys_hi_rsvd)) { mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); changed =3D true; } @@ -947,8 +949,12 @@ static unsigned long set_mtrr_state(void) =20 void mtrr_disable(void) { + struct msr val; + /* Save MTRR state */ - rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); + rdmsrq(MSR_MTRRdefType, val.q); + deftype_lo =3D val.l; + deftype_hi =3D val.h; =20 /* Disable MTRRs, and set the default type to uncached */ mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_h= i); @@ -1057,8 +1063,9 @@ int generic_validate_add_page(unsigned long base, uns= igned long size, =20 static int generic_have_wrcomb(void) { - unsigned long config, dummy; - rdmsr(MSR_MTRRcap, config, dummy); + u64 config; + + rdmsrq(MSR_MTRRcap, config); return config & MTRR_CAP_WC; } =20 diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 4b3d492..468c53b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -547,7 +547,7 @@ void __init mtrr_bp_init(void) { bool generic_mtrrs =3D cpu_feature_enabled(X86_FEATURE_MTRR); const char *why =3D "(not available)"; - unsigned long config, dummy; + unsigned long config; =20 phys_hi_rsvd =3D GENMASK(31, boot_cpu_data.x86_phys_bits - 32); =20 @@ -571,7 +571,7 @@ void __init mtrr_bp_init(void) if (mtrr_enabled()) { /* Get the number of variable MTRR ranges. */ if (mtrr_if =3D=3D &generic_mtrr_ops) - rdmsr(MSR_MTRRcap, config, dummy); + rdmsrq(MSR_MTRRcap, config); else config =3D mtrr_if->var_regs; num_var_ranges =3D config & MTRR_CAP_VCNT;