From nobody Sat Jul 25 05:31:08 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C1E439CCF3; Fri, 17 Jul 2026 09:42:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784281359; cv=none; b=M0uIwyHpU/BbNfqAQ2QGrMki3EUcXVCkRLXFOM73SW3LFFMaRzqw2P6j6RpXh6rq3F9TLOLPe9lHu4KOQKBb0cVWmwsP0VzOBllBjFZ5g91Ir4tieKR34X2RRyePAXvgpxv0vQnkeGXNhI9v1j+woqEGbbY07Io5axisRMS2Vac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784281359; c=relaxed/simple; bh=SxpRrEV6fXJ2D6zcyNTZTvrILRB7YWanVphfT/vKXqI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=lkc9nfz00rPj4Xo9DPCKWPbsNz0quWO4Kh1caSJbfctTbuu/YlLQQg9OWwa37MBYDL03u2jAqnU8IKSK0HU+pLO11Nhb3cqDmh4sBuIUaDP2qKOWUTQLKgmMiGfS4+CstRzxvcl5y58DMYX/ryejU+J8ZrAni1gl7dDdY4R//zk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=tz+XO8hd; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JN/ZFRML; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="tz+XO8hd"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JN/ZFRML" Date: Fri, 17 Jul 2026 09:42:35 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784281356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Psg9F1G58fRigZXizaxMJC+lELbGLU8HxTggamUXozw=; b=tz+XO8hdcY471r7lNRU5l+rrm9gHVb+mX9JRHPd+bro5XpUff9S0XduIooTVJRbYW7mqkt YKwDtm974mpEoM8/buldKrwgwfDocUSHVOUy1CUG55rvogSkMSPH+CabSjMVCKV4m7sU4v FbAvYlJaYtBg41UKnEiCQGlkO1OrI9GPEIaAiRKfAlS+qg2AxVXe5Hvb6BTaaPfgVXx2iD Sqmyi9FFQQMIS9NIlDqeTOLNmSESlT1EPhgRWNdGbpD1xP0rt3CivSbA23nu/2+ZCZs9xC EWIrjy06VHpGvfgrkaK5D+jq1Ln1D6QJteTMsgPXCkQJztZJOaABPc0Up3IL7A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784281356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Psg9F1G58fRigZXizaxMJC+lELbGLU8HxTggamUXozw=; b=JN/ZFRML1w0qH/3CfAM4p1TE1uQHPxqj0K4ov+GbPltqCcRZyoHglzbN8xjNOkB23En4me hXEMev3jbC8ERWAw== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/msr] x86/featctl: Stop using 32-bit MSR interfaces Cc: Juergen Gross , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260703112426.1763049-1-jgross@suse.com> References: <20260703112426.1763049-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178428135536.1844600.3852785488772100356.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/msr branch of tip: Commit-ID: f44da125bcecd78705ab506f6e18a4a5db1a35e1 Gitweb: https://git.kernel.org/tip/f44da125bcecd78705ab506f6e18a4a5d= b1a35e1 Author: Juergen Gross AuthorDate: Fri, 03 Jul 2026 13:24:26 +02:00 Committer: Ingo Molnar CommitterDate: Fri, 17 Jul 2026 11:30:36 +02:00 x86/featctl: Stop using 32-bit MSR interfaces The 32-bit MSR interfaces rdmsr() and rdmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross Signed-off-by: Ingo Molnar Cc: H. Peter Anvin Link: https://patch.msgid.link/20260703112426.1763049-1-jgross@suse.com --- arch/x86/kernel/cpu/feat_ctl.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c index d697572..10a9292 100644 --- a/arch/x86/kernel/cpu/feat_ctl.c +++ b/arch/x86/kernel/cpu/feat_ctl.c @@ -25,7 +25,8 @@ enum vmx_feature_leafs { =20 static void init_vmx_capabilities(struct cpuinfo_x86 *c) { - u32 supported, funcs, ept, vpid, ign, low, high; + struct msr val; + u32 supported, funcs, ept, vpid; =20 BUILD_BUG_ON(NVMXINTS !=3D NR_VMX_FEATURE_WORDS); =20 @@ -39,25 +40,31 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) * as they exist on any CPU that supports VMX, i.e. we want the WARN if * the RDMSR faults. */ - rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported); + rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q); + supported =3D val.h; c->vmx_capability[PRIMARY_CTLS] =3D supported; =20 - rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported); + rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &val.q); + supported =3D val.h; c->vmx_capability[SECONDARY_CTLS] =3D supported; =20 /* All 64 bits of tertiary controls MSR are allowed-1 settings. */ - rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high); - c->vmx_capability[TERTIARY_CTLS_LOW] =3D low; - c->vmx_capability[TERTIARY_CTLS_HIGH] =3D high; + rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &val.q); + c->vmx_capability[TERTIARY_CTLS_LOW] =3D val.l; + c->vmx_capability[TERTIARY_CTLS_HIGH] =3D val.h; =20 - rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported); - rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs); + rdmsrq(MSR_IA32_VMX_PINBASED_CTLS, val.q); + supported =3D val.h; + rdmsrq_safe(MSR_IA32_VMX_VMFUNC, &val.q); + funcs =3D val.h; =20 /* * Except for EPT+VPID, which enumerates support for both in a single * MSR, low for EPT, high for VPID. */ - rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, &ept, &vpid); + rdmsrq_safe(MSR_IA32_VMX_EPT_VPID_CAP, &val.q); + ept =3D val.l; + vpid =3D val.h; =20 /* Pin, EPT, VPID and VM-Func are merged into a single word. */ WARN_ON_ONCE(supported >> 16);