From nobody Sat Jul 25 05:29:25 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 388213C344D; Fri, 17 Jul 2026 09:26:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784280385; cv=none; b=ddLAbGCIDjXcFWQBKsGdAuiUuEV16+4LX7vGvRw4IpVg3vZoyUzC/+LL8nqypsbvRPsVfUKyxqlmLnRKess7gu5geumneV8+dSNEDkJZBJFiokN5nGeq5D/dPMkhtq3a7mWy+lDqKahl895bV9/LoUAY+RmhvhEttUb9t5Jjwj8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784280385; c=relaxed/simple; bh=+Ib7BecBfdnxpysQ+yrIbN0xzNK6C9QLspzUT8xO1Ss=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=sc36/bMLWDZk3CiAIFg0okhlWDjG4BgBxMGS4zwZKY42HB1LmJg++1mmHElOW8LMGQr4XbNHdhu9dRcjScu0uBaNm0/XdT5HeEDbBcBox+4SOyPNLVjxABzEk62FYhncUL5O03cpESZIU7lAXZuwlrYzDAYgv9gepUCRMyrmvtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0AiuBt83; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XwK/TYhc; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0AiuBt83"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XwK/TYhc" Date: Fri, 17 Jul 2026 09:26:18 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784280379; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OJPcWOzVLVGp+Drn632cayjbt/EETtR9rfC1xkU0Res=; b=0AiuBt83xB3TbOsQnWTfnJXvyxWZgwfg/tq+fG9M9y9ae58bNRM0izqou3Os4/RfBwofYA 91RCHXT/A9VadbdEmdQoP/q0ok810g53fmjNuzYslItinzCuLWSMzXJpfCxFZencbvHkRX 6UFIK+7N2sqKnCE5t4RD+5JWAvcV1R4XwYhLlZePn8/YKqzayLe8E507GIzrW9AOfHCeWc rXUJjuaom8VBCZ1VWH+yufFeRAfprXaMUHMmt5NCC7HhoUX7XsK64cg2Sq99fFdiKghegf EQ4RPriZR6YCIDehXO90Ij/P1qvzgP0p+EQcwap0JkS9YZZSxTy+8VTkRtQKGA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784280379; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OJPcWOzVLVGp+Drn632cayjbt/EETtR9rfC1xkU0Res=; b=XwK/TYhcWpleqlLtanCsH7g7lR+200fxMGZJQbz3mbCYHiaFm2T3dlROagzGfP+k2MuRNb bAhUJEpBVAAaZ6DA== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/msr] thermal/intel: Stop using 32-bit MSR interfaces Cc: Juergen Gross , Ingo Molnar , "Rafael J. Wysocki (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260703112232.1762925-1-jgross@suse.com> References: <20260703112232.1762925-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178428037821.1844600.884630130600591179.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/msr branch of tip: Commit-ID: cdf3ab55a9b95e7ac847177920d3e03ae4cf8b93 Gitweb: https://git.kernel.org/tip/cdf3ab55a9b95e7ac847177920d3e03ae= 4cf8b93 Author: Juergen Gross AuthorDate: Fri, 03 Jul 2026 13:22:32 +02:00 Committer: Ingo Molnar CommitterDate: Fri, 17 Jul 2026 10:26:49 +02:00 thermal/intel: Stop using 32-bit MSR interfaces The 32-bit MSR interfaces rdmsr(), wrmsr(), rdmsr_safe() and wrmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross Signed-off-by: Ingo Molnar Acked-by: Rafael J. Wysocki (Intel) Link: https://patch.msgid.link/20260703112232.1762925-1-jgross@suse.com --- drivers/thermal/intel/intel_tcc.c | 10 +-- drivers/thermal/intel/therm_throt.c | 76 +++++++++---------- drivers/thermal/intel/x86_pkg_temp_thermal.c | 32 +++----- 3 files changed, 56 insertions(+), 62 deletions(-) diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/inte= l_tcc.c index 59f70bb..d1fa3c6 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -185,7 +185,7 @@ int intel_tcc_get_tjmax(int cpu) int val, err; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.l, &msrval.h); + err =3D rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &msrval.q); else err =3D rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval.q); if (err) @@ -212,7 +212,7 @@ int intel_tcc_get_offset(int cpu) int err; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); + err =3D rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &val.q); else err =3D rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) @@ -245,7 +245,7 @@ int intel_tcc_set_offset(int cpu, int offset) return -EINVAL; =20 if (cpu < 0) - err =3D rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &val.l, &val.h); + err =3D rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &val.q); else err =3D rdmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &val.q); if (err) @@ -259,7 +259,7 @@ int intel_tcc_set_offset(int cpu, int offset) val.l |=3D offset << 24; =20 if (cpu < 0) - return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, val.l, val.h); + return wrmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, val.q); else return wrmsrq_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, val.q); } @@ -288,7 +288,7 @@ int intel_tcc_get_temp(int cpu, int *temp, bool pkg) return tjmax; =20 if (cpu < 0) - err =3D rdmsr_safe(msr, &val.l, &val.h); + err =3D rdmsrq_safe(msr, &val.q); else err =3D rdmsrq_safe_on_cpu(cpu, msr, &val.q); if (err) diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/th= erm_throt.c index 45a8ef4..1dfd449 100644 --- a/drivers/thermal/intel/therm_throt.c +++ b/drivers/thermal/intel/therm_throt.c @@ -722,8 +722,8 @@ void __init therm_lvt_init(void) void intel_init_thermal(struct cpuinfo_x86 *c) { unsigned int cpu =3D smp_processor_id(); + struct msr val; int tm2 =3D 0; - u32 l, h; =20 if (!intel_thermal_supported(c)) return; @@ -733,9 +733,9 @@ void intel_init_thermal(struct cpuinfo_x86 *c) * be some SMM goo which handles it, so we can't even put a handler * since it might be delivered via SMI already: */ - rdmsr(MSR_IA32_MISC_ENABLE, l, h); + rdmsrq(MSR_IA32_MISC_ENABLE, val.q); =20 - h =3D lvtthmr_init; + val.h =3D lvtthmr_init; /* * The initial value of thermal LVT entries on all APs always reads * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI @@ -746,11 +746,11 @@ void intel_init_thermal(struct cpuinfo_x86 *c) * BIOS has programmed on AP based on BSP's info we saved since BIOS * is always setting the same value for all threads/cores. */ - if ((h & APIC_DM_FIXED_MASK) !=3D APIC_DM_FIXED) + if ((val.h & APIC_DM_FIXED_MASK) !=3D APIC_DM_FIXED) apic_write(APIC_LVTTHMR, lvtthmr_init); =20 =20 - if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { + if ((val.l & MSR_IA32_MISC_ENABLE_TM1) && (val.h & APIC_DM_SMI)) { if (system_state =3D=3D SYSTEM_BOOTING) pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu); return; @@ -759,59 +759,55 @@ void intel_init_thermal(struct cpuinfo_x86 *c) /* early Pentium M models use different method for enabling TM2 */ if (cpu_has(c, X86_FEATURE_TM2)) { if (c->x86 =3D=3D 6 && (c->x86_model =3D=3D 9 || c->x86_model =3D=3D 13)= ) { - rdmsr(MSR_THERM2_CTL, l, h); - if (l & MSR_THERM2_CTL_TM_SELECT) + rdmsrq(MSR_THERM2_CTL, val.q); + if (val.l & MSR_THERM2_CTL_TM_SELECT) tm2 =3D 1; - } else if (l & MSR_IA32_MISC_ENABLE_TM2) + } else if (val.l & MSR_IA32_MISC_ENABLE_TM2) tm2 =3D 1; } =20 /* We'll mask the thermal vector in the lapic till we're ready: */ - h =3D THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; - apic_write(APIC_LVTTHMR, h); + val.h =3D THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; + apic_write(APIC_LVTTHMR, val.h); =20 thermal_intr_init_core_clear_mask(); thermal_intr_init_pkg_clear_mask(); =20 - rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); - if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) - wrmsr(MSR_IA32_THERM_INTERRUPT, - (l | (THERM_INT_LOW_ENABLE - | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h); - else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) - wrmsr(MSR_IA32_THERM_INTERRUPT, - l | (THERM_INT_LOW_ENABLE - | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); + rdmsrq(MSR_IA32_THERM_INTERRUPT, val.q); + if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) { + val.l |=3D THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE; + val.l &=3D ~THERM_INT_PLN_ENABLE; + } else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) + val.l |=3D THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE | + THERM_INT_PLN_ENABLE; else - wrmsr(MSR_IA32_THERM_INTERRUPT, - l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); + val.l |=3D THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE; + wrmsrq(MSR_IA32_THERM_INTERRUPT, val.q); =20 if (cpu_has(c, X86_FEATURE_PTS)) { - rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); - if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) - wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, - (l | (PACKAGE_THERM_INT_LOW_ENABLE - | PACKAGE_THERM_INT_HIGH_ENABLE)) - & ~PACKAGE_THERM_INT_PLN_ENABLE, h); - else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) - wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, - l | (PACKAGE_THERM_INT_LOW_ENABLE - | PACKAGE_THERM_INT_HIGH_ENABLE - | PACKAGE_THERM_INT_PLN_ENABLE), h); + rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q); + if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) { + val.l |=3D PACKAGE_THERM_INT_LOW_ENABLE | + PACKAGE_THERM_INT_HIGH_ENABLE; + val.l &=3D ~PACKAGE_THERM_INT_PLN_ENABLE; + } else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) + val.l |=3D PACKAGE_THERM_INT_LOW_ENABLE | + PACKAGE_THERM_INT_HIGH_ENABLE | + PACKAGE_THERM_INT_PLN_ENABLE; else - wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, - l | (PACKAGE_THERM_INT_LOW_ENABLE - | PACKAGE_THERM_INT_HIGH_ENABLE), h); + val.l |=3D PACKAGE_THERM_INT_LOW_ENABLE | + PACKAGE_THERM_INT_HIGH_ENABLE; + wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q); =20 if (cpu_has(c, X86_FEATURE_HFI)) { - rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); - wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, - l | PACKAGE_THERM_INT_HFI_ENABLE, h); + rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q); + wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, + val.q | PACKAGE_THERM_INT_HFI_ENABLE); } } =20 - rdmsr(MSR_IA32_MISC_ENABLE, l, h); - wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); + rdmsrq(MSR_IA32_MISC_ENABLE, val.q); + wrmsrq(MSR_IA32_MISC_ENABLE, val.q | MSR_IA32_MISC_ENABLE_TM1); =20 pr_info_once("CPU0: Thermal monitoring enabled (%s)\n", tm2 ? "TM2" : "TM1"); diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal= /intel/x86_pkg_temp_thermal.c index 688e04c..43fd5bd 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -51,8 +51,7 @@ MODULE_PARM_DESC(notify_delay_ms, struct zone_device { int cpu; bool work_scheduled; - u32 msr_pkg_therm_low; - u32 msr_pkg_therm_high; + u64 msr_pkg_therm; struct delayed_work work; struct thermal_zone_device *tzone; struct cpumask cpumask; @@ -186,28 +185,28 @@ static bool pkg_thermal_rate_control(void) static inline void enable_pkg_thres_interrupt(void) { u8 thres_0, thres_1; - u32 l, h; + struct msr val; =20 - rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); + rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q); /* only enable/disable if it had valid threshold value */ - thres_0 =3D (l & THERM_MASK_THRESHOLD0) >> THERM_SHIFT_THRESHOLD0; - thres_1 =3D (l & THERM_MASK_THRESHOLD1) >> THERM_SHIFT_THRESHOLD1; + thres_0 =3D (val.l & THERM_MASK_THRESHOLD0) >> THERM_SHIFT_THRESHOLD0; + thres_1 =3D (val.l & THERM_MASK_THRESHOLD1) >> THERM_SHIFT_THRESHOLD1; if (thres_0) - l |=3D THERM_INT_THRESHOLD0_ENABLE; + val.l |=3D THERM_INT_THRESHOLD0_ENABLE; if (thres_1) - l |=3D THERM_INT_THRESHOLD1_ENABLE; - wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); + val.l |=3D THERM_INT_THRESHOLD1_ENABLE; + wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q); } =20 /* Disable threshold interrupt on local package/cpu */ static inline void disable_pkg_thres_interrupt(void) { - u32 l, h; + struct msr val; =20 - rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); + rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q); =20 - l &=3D ~(THERM_INT_THRESHOLD0_ENABLE | THERM_INT_THRESHOLD1_ENABLE); - wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); + val.l &=3D ~(THERM_INT_THRESHOLD0_ENABLE | THERM_INT_THRESHOLD1_ENABLE); + wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, val.q); } =20 static void pkg_temp_thermal_threshold_work_fn(struct work_struct *work) @@ -357,8 +356,7 @@ static int pkg_temp_thermal_device_add(unsigned int cpu) goto out_unregister_tz; =20 /* Store MSR value for package thermal interrupt, to restore at exit */ - rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm_low, - zonedev->msr_pkg_therm_high); + rdmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm); =20 cpumask_set_cpu(cpu, &zonedev->cpumask); raw_spin_lock_irq(&pkg_temp_lock); @@ -426,8 +424,8 @@ static int pkg_thermal_cpu_offline(unsigned int cpu) if (lastcpu) { zones[topology_logical_die_id(cpu)] =3D NULL; /* After this point nothing touches the MSR anymore. */ - wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, - zonedev->msr_pkg_therm_low, zonedev->msr_pkg_therm_high); + wrmsrq(MSR_IA32_PACKAGE_THERM_INTERRUPT, + zonedev->msr_pkg_therm); } =20 /*