From nobody Sat Jul 25 18:07:53 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8868C3B9D9A; Wed, 15 Jul 2026 07:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784099726; cv=none; b=K06TrP3ZUjsgjWeHbTQBqRDQ9deLBDw+47Nwqll5zmxN/AnQrkjdDHvxG3h4sCJ9QrLwMHXmCqi6h++vQvZx4cVG4FHXi4n/E/9r8eZ/SUe5a/yap8D8mRRlW1wqhb97oNbz+yAYV5XXKxhI5vv2GHdLbQpYfoD5K/7Ec7Jshjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784099726; c=relaxed/simple; bh=ZwZ9ZrCu9BTNdXK/bMBYdw50tncwTRWo+t2tASKqtWM=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=iNxcP+vdaqPlodz7JSqCizr5Ogz6q8UJ/gb59t60ygsfXNupwFVfAs4ob/J+O/MgdWwYX3RrQoxhJtLZzJYUeN9RYevtvFnWxkHElHvQXtVg5ye3YoQk8pzruwtRGMYxTIaGh4tux99C+D5o+SXWO+O6Yz+saLF1Zdb3Ctlajto= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=eQGlzhiq; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=7ATLRIh4; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="eQGlzhiq"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="7ATLRIh4" Date: Wed, 15 Jul 2026 07:15:21 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784099722; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=51OU9iCHd7E89uRVyNuJ2AgaftKMJEX+frQqzowVk+0=; b=eQGlzhiq0pVTzh1Po2M/XIef24B9GZX0FSb42ESbqzbFo6/ETKnEBOFedoObcxAjpKMMx+ DGXbTowihWbsK0cPjH2FQ+upWSzeyeqriRJgA6fX97F8ENT8Tf3IsxoQaN6zOSCYJuas3S 8pJvqh1HE4OsWpU9vAYA5RTIlaImKlJIDkJCx9LNgMRI9YV8TzFOXT+TjuySfO7lTAnoK7 M0voMpR1TPmCr/ZLphyYLLILc5TB9QYzIGZ/jkk+0NemuKxMCKkqC6F3SWARS57Ni9KPCU 99YfIGDjJybmlm4lsmNsg8erDNINkq0jeZJvuKTzJXZH8f43ZINNUrGQ9gtv0A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784099722; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=51OU9iCHd7E89uRVyNuJ2AgaftKMJEX+frQqzowVk+0=; b=7ATLRIh45UMIeSMNCY1Xk1KA0XBY7qjYP/gxrYztfcGTtRhlJ2x494YDYot/PHDDf6XvrF lUwCdMR8f5pWFyDg== From: "tip-bot2 for Jinqian Yang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/gic-v3-its: Enable dynamic MSI-X allocation Cc: Jinqian Yang , Thomas Gleixner , Marc Zyngier , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260715035437.700601-1-yangjinqian1@huawei.com> References: <20260715035437.700601-1-yangjinqian1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178409972115.1844600.12412224038900203524.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 0d6a7c417983b36f0aa2a61bc650e8df04dd6ba8 Gitweb: https://git.kernel.org/tip/0d6a7c417983b36f0aa2a61bc650e8df0= 4dd6ba8 Author: Jinqian Yang AuthorDate: Wed, 15 Jul 2026 11:54:37 +08:00 Committer: Thomas Gleixner CommitterDate: Wed, 15 Jul 2026 09:10:45 +02:00 irqchip/gic-v3-its: Enable dynamic MSI-X allocation On ARM64 platforms with GICv3 ITS, VFIO PCI passthrough currently cannot dynamically allocate MSI-X vectors after MSI-X has been enabled. When QEMU needs to extend the vector range, it must disable MSI-X, free all interrupts, then re-enable with a larger allocation. This creates an interrupt loss window for already-active vectors. Consider HNS3 with RoCE: NIC and RDMA share one PCI device and ITS DeviceID, with MSI-X vectors partitioned as NIC (lower range) then RoCE (starting at base_vector =3D num_nic_msi). In VFIO passthrough, loading hns_roce after hns3 forces QEMU to tear down all interrupts before re-allocating the larger range. During this process, NIC interrupts may be lost. Testing confirmed that this occasionally occurs, causing the network port reset to fail. This appears to be unavoidable, as it's a standard approach adopted by all network card vendors. On Hisilicon HIP09 (ARM64, GICv3/GICv4.1) with latest upstream kernel and QEMU 8.2. VFIO passthrough of HNS3 NIC to VM: load both hns3 and hns_roce_hw_v2 drivers and trigger FLR, this bug will occur occasionally. After enabling dynamic MSIX allocation, this bug no longer occurs. When dynamic MSI-X allocatiojn support is enabled, adding a new vector only inserts a new entry, existing entries are untouched, so already-active vectors are unaffected. The ITTs are sized to hardware size at MSI-X domain creation time. so there is always sufficient space for any vector index that may be dynamiclly allocated later. So the ITT never needs to be resized at runtime. The dynamic allocation path uses the already initialized ITT and allocates a free entry, which means no existing vector is affected. Signed-off-by: Jinqian Yang Signed-off-by: Thomas Gleixner Reviewed-by: Marc Zyngier Link: https://patch.msgid.link/20260715035437.700601-1-yangjinqian1@huawei.= com --- drivers/irqchip/irq-gic-its-msi-parent.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq= -gic-its-msi-parent.c index b925710..b2b9d20 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -18,7 +18,8 @@ =20 #define ITS_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ MSI_FLAG_PCI_MSIX | \ - MSI_FLAG_MULTI_PCI_MSI) + MSI_FLAG_MULTI_PCI_MSI | \ + MSI_FLAG_PCI_MSIX_ALLOC_DYN) =20 static int its_translate_frame_address(struct fwnode_handle *msi_node, phy= s_addr_t *pa) {