From nobody Sat Jun 13 23:45:11 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99E7C1A6817; Sat, 13 Jun 2026 14:33:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781361199; cv=none; b=axEasOY85RV9JAXFDWv8j1fwV7grbVCuv7I4x9pvUW43beIDQ34W9p17S3lBxv8Z+xSGDpShp59fe2BB8sRRi4X2OO9IAv7iQAajnD2d88dvyKF3tAQLrKLc04b1Xj00i68fG7tg7KUSxTt4gfMZIMV0PIkJ1L506FuRnBCtVKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781361199; c=relaxed/simple; bh=TLGwo2GfUAm5Jcv5UjZnvW7/vzOWtDtWn3gxlROCB9c=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=sc1EHaXnjXq2ZVIzP/B0UO99YALsX/qvc1RyiiSmIEJ7TlRYpoSgRsWSNWidFqzB2k4s8ozLmjMsaMt1s6HyJqhuW2NrhpSBARnducB44O84Fo1tI3aKAD280cq6JMjSV1dhL9c3gZk2Mn2/iNiFkfls9KIqBZdvkATsyOKxpYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BEo4mkcQ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QETv4MoO; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BEo4mkcQ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QETv4MoO" Date: Sat, 13 Jun 2026 14:33:14 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1781361195; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ToC9PTTMXeTxf3uYd4Z6gApKcb+AqDVJCyKTy1roCpE=; b=BEo4mkcQG7bEUo8MQcyVpClXVfLtZLEYPieUWYioq/GuDKxtC9+Wj4w9gIxH1CDB4D4RrI XlcP7oodKFhuWL4zdmORK0DD3o9CrcLbgEs7JEqoyAXMXbXonIRQiMOHWFtfM98728TdNB QpolsMveiquCyhZG4xTGQ/jkpLTOG85wE3J1Ibq8BvjI5LJ19nKg0Gw4BiSrnMHaQWC86t 5JHwkQTMMC334qO2/6CID2tWYbPMablCVVbAFKqcNqE0cO5lbtN2FHX0Emc3Fr52xgrakp xQCbrlRcv0Nf6HduinBhqP7XaW3RLs7Wnq9K+C964i4i5yvr2PpeG0dXiO8veg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1781361195; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ToC9PTTMXeTxf3uYd4Z6gApKcb+AqDVJCyKTy1roCpE=; b=QETv4MoOPe1l6gz8IkhQAwaPIlhVBPyskWzwCb/Qb8+n9AonhV3V7dFefKHbTTIuLcLYDr pFkxrW1gnlFxfgCw== From: "tip-bot2 for Michal Piekos" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/clocksource] clocksource/drivers/sun5i: Add D1 hstimer support Cc: Michal Piekos , Daniel Lezcano , "Chen-Yu Tsai" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260428-h616-t113s-hstimer-v3-2-7e02178a93ee@mmpsystems.pl> References: <20260428-h616-t113s-hstimer-v3-2-7e02178a93ee@mmpsystems.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178136119403.1650852.9678703796149009889.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the timers/clocksource branch of = tip: Commit-ID: f182fa740218dec7ead6275b2e096da1642272b5 Gitweb: https://git.kernel.org/tip/f182fa740218dec7ead6275b2e096da16= 42272b5 Author: Michal Piekos AuthorDate: Tue, 28 Apr 2026 18:26:59 +02:00 Committer: Daniel Lezcano CommitterDate: Wed, 06 May 2026 13:05:59 +02:00 clocksource/drivers/sun5i: Add D1 hstimer support D1 high speed timer differs from existing timer-sun5i by register base offset. Add sunxi quirks to handle D1 specific offset. Add D1 compatible string to OF match table. Signed-off-by: Michal Piekos Signed-off-by: Daniel Lezcano Reviewed-by: Chen-Yu Tsai Link: https://patch.msgid.link/20260428-h616-t113s-hstimer-v3-2-7e02178a93e= e@mmpsystems.pl --- drivers/clocksource/timer-sun5i.c | 84 +++++++++++++++++++++++------- 1 file changed, 65 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-= sun5i.c index d7e0129..6ab300d 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -18,21 +18,30 @@ #include #include =20 -#define TIMER_IRQ_EN_REG 0x00 +#define TIMER_IRQ_EN_REG 0x00 #define TIMER_IRQ_EN(val) BIT(val) -#define TIMER_IRQ_ST_REG 0x04 -#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10) +#define TIMER_IRQ_ST_REG 0x04 +#define TIMER_CTL_REG(val, offset) (0x20 * (val) + 0x10 + (offset)) #define TIMER_CTL_ENABLE BIT(0) #define TIMER_CTL_RELOAD BIT(1) #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) #define TIMER_CTL_ONESHOT BIT(7) -#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14) -#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18) -#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c) -#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20) +#define TIMER_INTVAL_LO_REG(val, offset) (0x20 * (val) + 0x14 + (offset)) +#define TIMER_INTVAL_HI_REG(val, offset) (0x20 * (val) + 0x18 + (offset)) +#define TIMER_CNTVAL_LO_REG(val, offset) (0x20 * (val) + 0x1c + (offset)) +#define TIMER_CNTVAL_HI_REG(val, offset) (0x20 * (val) + 0x20 + (offset)) =20 #define TIMER_SYNC_TICKS 3 =20 +/** + * struct sunxi_timer_quirks - Differences between SoC variants. + * + * @from_ctl_base_offset: offset applied from ctl register onwards + */ +struct sunxi_timer_quirks { + u32 from_ctl_base_offset; +}; + struct sun5i_timer { void __iomem *base; struct clk *clk; @@ -40,6 +49,7 @@ struct sun5i_timer { u32 ticks_per_jiffy; struct clocksource clksrc; struct clock_event_device clkevt; + const struct sunxi_timer_quirks *quirks; }; =20 #define nb_to_sun5i_timer(x) \ @@ -57,28 +67,36 @@ struct sun5i_timer { */ static void sun5i_clkevt_sync(struct sun5i_timer *ce) { - u32 old =3D readl(ce->base + TIMER_CNTVAL_LO_REG(1)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + u32 old =3D readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset)); =20 - while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICK= S) + while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset))) < + TIMER_SYNC_TICKS) cpu_relax(); } =20 static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer) { - u32 val =3D readl(ce->base + TIMER_CTL_REG(timer)); - writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + u32 val =3D readl(ce->base + TIMER_CTL_REG(timer, offset)); + + writel(val & ~TIMER_CTL_ENABLE, + ce->base + TIMER_CTL_REG(timer, offset)); =20 sun5i_clkevt_sync(ce); } =20 static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 = delay) { - writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + + writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer, offset)); } =20 static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool= periodic) { - u32 val =3D readl(ce->base + TIMER_CTL_REG(timer)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + u32 val =3D readl(ce->base + TIMER_CTL_REG(timer, offset)); =20 if (periodic) val &=3D ~TIMER_CTL_ONESHOT; @@ -86,7 +104,7 @@ static void sun5i_clkevt_time_start(struct sun5i_timer *= ce, u8 timer, bool perio val |=3D TIMER_CTL_ONESHOT; =20 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - ce->base + TIMER_CTL_REG(timer)); + ce->base + TIMER_CTL_REG(timer, offset)); } =20 static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt) @@ -141,8 +159,9 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void = *dev_id) static u64 sun5i_clksrc_read(struct clocksource *clksrc) { struct sun5i_timer *cs =3D clksrc_to_sun5i_timer(clksrc); + u32 offset =3D cs->quirks->from_ctl_base_offset; =20 - return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1)); + return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1, offset)); } =20 static int sun5i_rate_cb(struct notifier_block *nb, @@ -173,12 +192,13 @@ static int sun5i_setup_clocksource(struct platform_de= vice *pdev, unsigned long rate) { struct sun5i_timer *cs =3D platform_get_drvdata(pdev); + u32 offset =3D cs->quirks->from_ctl_base_offset; void __iomem *base =3D cs->base; int ret; =20 - writel(~0, base + TIMER_INTVAL_LO_REG(1)); + writel(~0, base + TIMER_INTVAL_LO_REG(1, offset)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - base + TIMER_CTL_REG(1)); + base + TIMER_CTL_REG(1, offset)); =20 cs->clksrc.name =3D pdev->dev.of_node->name; cs->clksrc.rating =3D 340; @@ -237,6 +257,7 @@ static int sun5i_setup_clockevent(struct platform_devic= e *pdev, =20 static int sun5i_timer_probe(struct platform_device *pdev) { + const struct sunxi_timer_quirks *quirks; struct device *dev =3D &pdev->dev; struct sun5i_timer *st; struct reset_control *rstc; @@ -273,11 +294,18 @@ static int sun5i_timer_probe(struct platform_device *= pdev) return -EINVAL; } =20 + quirks =3D of_device_get_match_data(&pdev->dev); + if (!quirks) { + dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); + return -ENODEV; + } + st->base =3D timer_base; st->ticks_per_jiffy =3D DIV_ROUND_UP(rate, HZ); st->clk =3D clk; st->clk_rate_cb.notifier_call =3D sun5i_rate_cb; st->clk_rate_cb.next =3D NULL; + st->quirks =3D quirks; =20 ret =3D devm_clk_notifier_register(dev, clk, &st->clk_rate_cb); if (ret) { @@ -314,9 +342,27 @@ static void sun5i_timer_remove(struct platform_device = *pdev) clocksource_unregister(&st->clksrc); } =20 +static const struct sunxi_timer_quirks sun5i_sun7i_hstimer_quirks =3D { + .from_ctl_base_offset =3D 0x0, +}; + +static const struct sunxi_timer_quirks sun20i_d1_hstimer_quirks =3D { + .from_ctl_base_offset =3D 0x10, +}; + static const struct of_device_id sun5i_timer_of_match[] =3D { - { .compatible =3D "allwinner,sun5i-a13-hstimer" }, - { .compatible =3D "allwinner,sun7i-a20-hstimer" }, + { + .compatible =3D "allwinner,sun5i-a13-hstimer", + .data =3D &sun5i_sun7i_hstimer_quirks, + }, + { + .compatible =3D "allwinner,sun7i-a20-hstimer", + .data =3D &sun5i_sun7i_hstimer_quirks, + }, + { + .compatible =3D "allwinner,sun20i-d1-hstimer", + .data =3D &sun20i_d1_hstimer_quirks, + }, {}, }; MODULE_DEVICE_TABLE(of, sun5i_timer_of_match);