From nobody Sat Jun 13 23:26:12 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C96A311592; Sat, 13 Jun 2026 14:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781361202; cv=none; b=uCoyMOYE2//1E9i2CicJBVGaypXNWO4jzFrmrQoALpGVJqJNDzkeq9nvtjts/Ns4ROUM5gf/tn+6r04vLTfGEPgU37jE9pvm/uwGAMdtRRxr1mtwaNNeITx9qoFl11tEFcOIp+mxBHcfxU+mxqd1TTYHIdn/Eq0LLUYXUeZNlDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781361202; c=relaxed/simple; bh=Y76CKxuAT2LFsbrZz+Jbd087x+ZDlblgqCVLiv/Gn1E=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=nzt1jw41i+e1fGNtd43zOVjMCCOv8agP88SEtFxTpEOjqH/C/5nb0nE4W0ZufQFu4GWNGVU7hhvQZaqqnvv0b/EI/bU8Oi6CcJOUPuCUBAdm7v126+dZNtAy+l+ij+iTTlIQkwwTwYvcTRkc42CcfCqaHXM46A54QhFuT275jro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=u9J4rcuH; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Z/UztGYh; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="u9J4rcuH"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Z/UztGYh" Date: Sat, 13 Jun 2026 14:33:08 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1781361190; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M0FTQPr7Xwdqp+fg7o3NqBr2SsTHWCagSdl5D8U/ivo=; b=u9J4rcuHOG7yNXPJM6JX6mbCiMgw1DqkJTKdqx62ExpGCqHdsKLYTyOg5kDwD0Abwj9KTV twu2iCqcqy1EzNQIRx3qAlsrU3J0PygH1WPB6Auxzpg3MJDoSyvGfc9AIRRr7fas4MOYnN xBlPEY4+MByYCP+goyZoaLQ4a3FcVSzkiFjXFLvMNvLyzDHEAskUq24DYgHCI2vyLIjrA6 m/98fOCnjBhjK4dOyUD4Byvm9QS7GYs3T9QyOtInfcaFxaPcDaQHU43dopc5mPYAUkfU4G lsj3Scq6bAu9IwoJSifcea3qy65zWQy4UPgKlx/rZW247VxVQJKZI+FV748XUA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1781361190; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M0FTQPr7Xwdqp+fg7o3NqBr2SsTHWCagSdl5D8U/ivo=; b=Z/UztGYhuOxR3lu4X9vNnISwcUsrBogdVr6pQcF1s9h2EA2LqU9T9g5hjyO7VRo0KHui3b vgu37bazqZEWb0DQ== From: "tip-bot2 for Marc Zyngier" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/clocksource] dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description Cc: Marc Zyngier , Daniel Lezcano , "Rob Herring (Arm)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260523140242.586031-5-maz@kernel.org> References: <20260523140242.586031-5-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178136118847.1650852.12884345375727402801.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the timers/clocksource branch of = tip: Commit-ID: 6951e870868d0b4bc385cbc851b871effa595330 Gitweb: https://git.kernel.org/tip/6951e870868d0b4bc385cbc851b871eff= a595330 Author: Marc Zyngier AuthorDate: Sat, 23 May 2026 15:02:29 +01:00 Committer: Daniel Lezcano CommitterDate: Wed, 03 Jun 2026 09:53:39 +02:00 dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt descript= ion The arm,arch_timer DT binding is extremely imprecise in describing the requirements for interrupts. Follow the architecture by making it explicit that: - the EL1 secure timer irq is required if EL3 is implemented - the EL1 physical timer irq is always required - the EL1 virtual timer irq is always required - the EL2 physical timer irq is required if EL2 is implemented - the EL2 virtual timer irq is required if FEAT_VHE is implemented The consequence of the above is that the minimum number of interrupts to be described is 2, and not 1. Finally, clean up the description which made the assumption that the timers are plugged into a GIC (unfortunately, that's not always true), drop the MMIO nonsense that has long be moved to a separate binding, and use the architectural terminology to describe the various interrupts. Signed-off-by: Marc Zyngier Signed-off-by: Daniel Lezcano Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260523140242.586031-5-maz@kernel.org --- Documentation/devicetree/bindings/timer/arm,arch_timer.yaml | 21 ++----- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/= Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index c5fc3b6..c65e48a 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -10,13 +10,8 @@ maintainers: - Marc Zyngier - Mark Rutland description: |+ - ARM cores may have a per-core architected timer, which provides per-cpu = timers, - or a memory mapped architected timer, which provides up to 8 frames with= a - physical and optional virtual timer per frame. - - The per-core architected timer is attached to a GIC to deliver its - per-processor interrupts via PPIs. The memory mapped timer is attached t= o a GIC - to deliver its interrupts via SPIs. + The per-core architected timer is expected to deliver per-CPU interrupts + (commonly to a GIC to deliver its per-processor interrupts as PPIs). =20 properties: compatible: @@ -33,13 +28,13 @@ properties: - const: arm,armv7-timer =20 interrupts: - minItems: 1 + minItems: 2 items: - - description: secure timer irq - - description: non-secure timer irq - - description: virtual timer irq - - description: hypervisor timer irq - - description: hypervisor virtual timer irq + - description: EL1 secure physical timer irq, if EL3 is implemented + - description: EL1 non-secure physical timer irq + - description: EL1 virtual timer irq + - description: EL2 physical timer irq, if EL2 is implemented + - description: EL2 virtual timer irq, if FEAT_VHE is implemented =20 interrupt-names: oneOf: