From nobody Sat Jun 13 23:22:56 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80F5B2C0274; Sat, 13 Jun 2026 14:33:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781361184; cv=none; b=MGnAT+QaBQ8nZ79UWH5lWN5+b9Ssf6o0VaXwveGsaIW6VsW58hnun8frFhSx25JP0MsIeJ4c80gMJiVLA6RvDjO/b/JMDoLnfYFCgYKV4o3rnneHZU8cgWnRDih88X0cXwb72egf7DLs0iFxhoii1voWPA6Xq15/Bkz+LK36Z3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781361184; c=relaxed/simple; bh=3kkXCruxX6VVzm2QFsAPs1Nhn2eC+VYbY+ukGrVuZbc=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=lijlTmcmD1NiBQbBzkXYPn4wcZKUVRSvKh3bzZ4I8ZMDhSeuvosmUFFVbcSCWlpuZe22z9Eg24X8va261IyGvUqSO3uwacDfbjPs7MkuZii7EcDbeKXcfkvvEub6wV/XuGTnHp2r7W9HctD1nMZsTAopL0NHlUn0Lmu9/f5ov5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ATHteuqf; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RIYQ5QVk; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ATHteuqf"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RIYQ5QVk" Date: Sat, 13 Jun 2026 14:33:00 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1781361182; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xdNRc6S5C4NpSEE29EsAVraQY3nkW1Nt3Ia/ve5I2Bw=; b=ATHteuqfe1JfVP+I5ZhfSBzNGjMccEv0cDDkmjN6M0uLH+ET2eQie/KrmW6012P7Jsw90U 42qqoyrRftc/4Yesozu8WR0ghC/Bd/fLrDskDdPFV57EIJNocVl8tvKU0csLBKRygOnE59 qg7q+niqWqnKr73MriryvyuCbIPpQ/TF1zRAIcII0uz0skjkzYMLbGnEVJZrev3KDMdCan 9T6G4OzxTlEGv7hP+P5kWGFfb6/7Y7zy0UD1odx7F4Sj45/IYdUwTrwqfpsANUYP03Kp8e G61HX5bB6cW+RR+axZXU6a13dA7L3WBjB87yEe5P6OBH01wGIYADbVyek3SIVQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1781361182; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xdNRc6S5C4NpSEE29EsAVraQY3nkW1Nt3Ia/ve5I2Bw=; b=RIYQ5QVk8dLq2TXMhgb4mhTxlGSoDX/D0eoAhB00Tb2F+r5Ra0C33+waZlfWfLn6Bq9h1Y PFfuZSvBEiMla7CQ== From: "tip-bot2 for Kartik Rajput" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/clocksource] clocksource/drivers/timer-tegra186: Register all accessible watchdog timers Cc: Kartik Rajput , Daniel Lezcano , Jon Hunter , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260507154557.2082697-4-kkartik@nvidia.com> References: <20260507154557.2082697-4-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178136118060.1650852.14598819866181949117.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the timers/clocksource branch of = tip: Commit-ID: 5eb5d8eaeacf09f924458dacd590b7f9b1607cea Gitweb: https://git.kernel.org/tip/5eb5d8eaeacf09f924458dacd590b7f9b= 1607cea Author: Kartik Rajput AuthorDate: Thu, 07 May 2026 21:15:56 +05:30 Committer: Daniel Lezcano CommitterDate: Wed, 10 Jun 2026 07:25:40 +02:00 clocksource/drivers/timer-tegra186: Register all accessible watchdog timers Tegra186+ SoCs expose multiple watchdog timers, but the driver only registers WDT(0). Iterate over num_wdts and, for each WDT, check the SCR (firewall) registers in the TKE block to determine whether Linux has read and write access. Register the watchdogs that are accessible. Signed-off-by: Kartik Rajput Signed-off-by: Daniel Lezcano Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260507154557.2082697-4-kkartik@nvidia.com --- drivers/clocksource/timer-tegra186.c | 61 ++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/tim= er-tegra186.c index fd82a73..dd1d1a0 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -57,6 +57,13 @@ #define WDTUR 0x00c #define WDTUR_UNLOCK_PATTERN 0x0000c45a =20 +/* WDT security configuration registers */ +#define WDTSCR(x) (0xf02c + (x) * 4) +#define WDTSCR_SEC_WEN BIT(28) +#define WDTSCR_SEC_REN BIT(27) +#define WDTSCR_SEC_G1W BIT(9) +#define WDTSCR_SEC_G1R BIT(1) + struct tegra186_timer_soc { unsigned int num_timers; unsigned int num_wdts; @@ -89,7 +96,7 @@ struct tegra186_timer { struct device *dev; void __iomem *regs; =20 - struct tegra186_wdt *wdt; + struct tegra186_wdt **wdts; struct clocksource usec; struct clocksource tsc; struct clocksource osc; @@ -298,6 +305,23 @@ static const struct watchdog_ops tegra186_wdt_ops =3D { .get_timeleft =3D tegra186_wdt_get_timeleft, }; =20 +static bool tegra186_wdt_is_accessible(struct tegra186_timer *tegra, unsig= ned int index) +{ + u32 value; + + value =3D readl_relaxed(tegra->regs + WDTSCR(index)); + + /* Check OS write access if write blocking is enabled. */ + if ((value & WDTSCR_SEC_WEN) && !(value & WDTSCR_SEC_G1W)) + return false; + + /* Check OS read access if read blocking is enabled. */ + if ((value & WDTSCR_SEC_REN) && !(value & WDTSCR_SEC_G1R)) + return false; + + return true; +} + static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *teg= ra, unsigned int index) { @@ -424,6 +448,7 @@ static int tegra186_timer_probe(struct platform_device = *pdev) { struct device *dev =3D &pdev->dev; struct tegra186_timer *tegra; + unsigned int i; int err; =20 tegra =3D devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL); @@ -442,12 +467,20 @@ static int tegra186_timer_probe(struct platform_devic= e *pdev) if (err < 0) return err; =20 - /* create a watchdog using a preconfigured timer */ - tegra->wdt =3D tegra186_wdt_create(tegra, 0); - if (IS_ERR(tegra->wdt)) { - err =3D PTR_ERR(tegra->wdt); - dev_err(dev, "failed to create WDT: %d\n", err); - return err; + tegra->wdts =3D devm_kcalloc(dev, tegra->soc->num_wdts, sizeof(*tegra->wd= ts), GFP_KERNEL); + if (!tegra->wdts) + return -ENOMEM; + + for (i =3D 0; i < tegra->soc->num_wdts; i++) { + if (!tegra186_wdt_is_accessible(tegra, i)) { + dev_warn(dev, "WDT%u is not accessible\n", i); + continue; + } + + tegra->wdts[i] =3D tegra186_wdt_create(tegra, i); + if (IS_ERR(tegra->wdts[i])) + return dev_err_probe(dev, PTR_ERR(tegra->wdts[i]), + "failed to create WDT%u\n", i); } =20 err =3D tegra186_timer_tsc_init(tegra); @@ -489,9 +522,12 @@ static void tegra186_timer_remove(struct platform_devi= ce *pdev) static int __maybe_unused tegra186_timer_suspend(struct device *dev) { struct tegra186_timer *tegra =3D dev_get_drvdata(dev); + unsigned int i; =20 - if (watchdog_active(&tegra->wdt->base)) - tegra186_wdt_disable(tegra->wdt); + for (i =3D 0; i < tegra->soc->num_wdts; i++) { + if (tegra->wdts[i] && watchdog_active(&tegra->wdts[i]->base)) + tegra186_wdt_disable(tegra->wdts[i]); + } =20 return 0; } @@ -499,9 +535,12 @@ static int __maybe_unused tegra186_timer_suspend(struc= t device *dev) static int __maybe_unused tegra186_timer_resume(struct device *dev) { struct tegra186_timer *tegra =3D dev_get_drvdata(dev); + unsigned int i; =20 - if (watchdog_active(&tegra->wdt->base)) - tegra186_wdt_enable(tegra->wdt); + for (i =3D 0; i < tegra->soc->num_wdts; i++) { + if (tegra->wdts[i] && watchdog_active(&tegra->wdts[i]->base)) + tegra186_wdt_enable(tegra->wdts[i]); + } =20 return 0; }