From nobody Mon Jun 8 07:26:02 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6FB03B71B2; Fri, 5 Jun 2026 09:37:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780652224; cv=none; b=BgJZopnscQzRJZhLFIrb5kDSO70Z/3frx9rdCSQDnqn1Z6bV4kdIrCKw6WZ3VvfMSYU9MgvdyGSrlk9YengcVU/RajC/1GaB6UN5Eqf+AqnNETRMFCI7uOp9JZ+2w69ifDnkZSvISGlM188hIXQS60M8DLkG/fhjwqGWg0IatEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780652224; c=relaxed/simple; bh=L1TmBxfiYKpR9dklN46IhKQrWWNxMKSeOGIi5jYpgQg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=cBZ2whYZW98T1SFP4syafAWkeRSNvhky1rgQ/TJap2GVH8AjQ1YlKC5ghTc751/exut/HU3tPZSSjumxTXUTkIHu9YNtSDkyMB21RCoWMCe1QW/tcsswjzaESy+fZGl0pAG4JShn4+jwyNDbXNYEp7gyrxXZjBv8UPKl4EIVWtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Ow4QEIfG; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oVKMhe8c; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Ow4QEIfG"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oVKMhe8c" Date: Fri, 05 Jun 2026 09:37:00 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780652222; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xulXUyuXVTtgQJcLn2wSDl1KwsWd6e28NYaeHE171so=; b=Ow4QEIfGMV6XGpdGkGfjsr1CH3NRpwOajj5cjeqNyZzNqfNn5tPPEuNuH7+9kUAi5u+uVs ix8YpTBAzxdYUif65hkcdOP9rWXt5Tjwe/XH9JjC+5gQplMGkANf4G9zeY6in/BAQGG02k lArmACl+0Y/7fsv/6yDWTt6ScAHLs5Uh1XDC6wjc4CKu1oxNuVRLikeMKyykdzZScElzZO BeCXlUl3ggQgG1yzzf+jhwcXDstUJrlho3JyRJSFb9H97wMPJNa8QRKRp2SLqp7NG2ypSN kI3z3kqKxXbWQeB5isgnJ7M9HFzCLOKd3devHkizH/Sqwn7H5gCko2p268oX6g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780652222; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xulXUyuXVTtgQJcLn2wSDl1KwsWd6e28NYaeHE171so=; b=oVKMhe8cwjRA/t6PTDxaxOCHjGqqlUBplWz76YRlfdFpRP27aD/3Oc4slirABZeF+f+rUY 5fPnYFKs/0FMEdAQ== From: "tip-bot2 for Markus Stockhausen" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/irq-realtek-rtl: Add/simplify register helpers Cc: Markus Stockhausen , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260604182506.1113440-2-markus.stockhausen@gmx.de> References: <20260604182506.1113440-2-markus.stockhausen@gmx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178065222056.710.9651322639230065423.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 167883f75f83088a2b32c85ce5e3d0cd1cef157b Gitweb: https://git.kernel.org/tip/167883f75f83088a2b32c85ce5e3d0cd1= cef157b Author: Markus Stockhausen AuthorDate: Thu, 04 Jun 2026 20:25:05 +02:00 Committer: Thomas Gleixner CommitterDate: Fri, 05 Jun 2026 11:35:10 +02:00 irqchip/irq-realtek-rtl: Add/simplify register helpers The Realtek interrupt controller has two important registers that are used by the driver in several places - GIMR: global interrupt mask register - IRR: Interrupt routing registers The usage of these registers is very inconsistent. GIMR is addressed directly while IRR has a helper that needs a macro as an input. Harmonize this by providing consistent helpers that improve code readability. The callers of these helpers use classic lock/unlock functions and sometimes use the wrong locking helper. E.g. irqsave variants are used in mask/unmask although not needed. Adapt and fix the surrounding call locations. Signed-off-by: Markus Stockhausen Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260604182506.1113440-2-markus.stockhausen@= gmx.de --- drivers/irqchip/irq-realtek-rtl.c | 64 +++++++++++++++--------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realte= k-rtl.c index 942c1f8..f490fb8 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -37,10 +37,29 @@ static void __iomem *realtek_ictl_base; #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) #define IRR_SHIFT(idx) ((idx * 4) % 32) =20 -static void write_irr(void __iomem *irr0, int idx, u32 value) +static inline void enable_gimr(unsigned int hw_irq) { - unsigned int offset =3D IRR_OFFSET(idx); - unsigned int shift =3D IRR_SHIFT(idx); + u32 gimr; + + gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr |=3D BIT(hw_irq); + writel(gimr, REG(RTL_ICTL_GIMR)); +} + +static inline void disable_gimr(unsigned int hw_irq) +{ + u32 gimr; + + gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr &=3D ~BIT(hw_irq); + writel(gimr, REG(RTL_ICTL_GIMR)); +} + +static void write_irr(int hw_irq, u32 value) +{ + void __iomem *irr0 =3D REG(RTL_ICTL_IRR0); + unsigned int offset =3D IRR_OFFSET(hw_irq); + unsigned int shift =3D IRR_SHIFT(hw_irq); u32 irr; =20 irr =3D readl(irr0 + offset) & ~(0xf << shift); @@ -50,30 +69,14 @@ static void write_irr(void __iomem *irr0, int idx, u32 = value) =20 static void realtek_ictl_unmask_irq(struct irq_data *i) { - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&irq_lock, flags); - - value =3D readl(REG(RTL_ICTL_GIMR)); - value |=3D BIT(i->hwirq); - writel(value, REG(RTL_ICTL_GIMR)); - - raw_spin_unlock_irqrestore(&irq_lock, flags); + guard(raw_spinlock)(&irq_lock); + enable_gimr(i->hwirq); } =20 static void realtek_ictl_mask_irq(struct irq_data *i) { - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&irq_lock, flags); - - value =3D readl(REG(RTL_ICTL_GIMR)); - value &=3D ~BIT(i->hwirq); - writel(value, REG(RTL_ICTL_GIMR)); - - raw_spin_unlock_irqrestore(&irq_lock, flags); + guard(raw_spinlock)(&irq_lock); + disable_gimr(i->hwirq); } =20 static struct irq_chip realtek_ictl_irq =3D { @@ -84,13 +87,10 @@ static struct irq_chip realtek_ictl_irq =3D { =20 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_= t hw) { - unsigned long flags; - irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); =20 - raw_spin_lock_irqsave(&irq_lock, flags); - write_irr(REG(RTL_ICTL_IRR0), hw, 1); - raw_spin_unlock_irqrestore(&irq_lock, flags); + guard(raw_spinlock_irqsave)(&irq_lock); + write_irr(hw, 1); =20 return 0; } @@ -127,7 +127,6 @@ static int __init realtek_rtl_of_init(struct device_nod= e *node, struct device_no { struct of_phandle_args oirq; struct irq_domain *domain; - unsigned int soc_irq; int parent_irq; =20 realtek_ictl_base =3D of_iomap(node, 0); @@ -135,9 +134,10 @@ static int __init realtek_rtl_of_init(struct device_no= de *node, struct device_no return -ENXIO; =20 /* Disable all cascaded interrupts and clear routing */ - writel(0, REG(RTL_ICTL_GIMR)); - for (soc_irq =3D 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) - write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0); + for (unsigned int hw_irq =3D 0; hw_irq < RTL_ICTL_NUM_INPUTS; hw_irq++) { + disable_gimr(hw_irq); + write_irr(hw_irq, 0); + } =20 if (WARN_ON(!of_irq_count(node))) { /*