From nobody Mon Jun 8 07:24:45 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A70513B71B3; Fri, 5 Jun 2026 09:37:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780652225; cv=none; b=AVUCzvEfelRbALeEcYKiTKWEDnrUWKUr5vbuGi1o9ppZNDL89sLfDouB3pP8qv/t/GCf87zgShcwtGTUOBW/QfxUEM3kAjJUCiN3rYI7rhtUC45Qm1RyOPdeSGGQSy6u5yj3cpxol1s9EvXSW39JEWFNhKzn+e7m6zWEeBqA8RQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780652225; c=relaxed/simple; bh=51xrA7qvgq3s6hHSmTKbpC4fwKG+TR+8lax6mlc/+jk=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=GiGCYHpFPSeTzOQOX9eNbtJoP9mI2+rHix0JVdd7XGB20ibyh6NrIH0dASTLDWm0kDjJwpaGfhG47nJP5MVFMdG+OTIYDoZrQ542wf9DvMShRnF8Yx6jlJQLw7g28TEKwizO/mlB8oL74E7nvJL1IEUY5YH7h7UW6A4UzqeOXF8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CbfZ2EBm; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1h5vRYP6; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CbfZ2EBm"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1h5vRYP6" Date: Fri, 05 Jun 2026 09:36:58 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780652220; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4NVMRo8naU1n4HF6MKYBUtjyWxQw5YbxqDRQuQoeDpE=; b=CbfZ2EBmc3F+4mOvP0Y8NRF+Xp4Z3qY4sO0iCTQZV8SnObD0Qtx88fF/Qer3Ot05HQGgKg NqcyO6xZOYVwC2156zACzglxDiR0/qjmVc1Cwn/M7gwdA9Lek9BfjPR0wCl3QNrmCPG149 4Q5RUwLEDu2yqLsXdGNZQX2dYlr1v8c37oGyUiUR0FV8CihUUZdCVTe5m+lzZkLQtV/el9 FyG/PEqUlxBkKVa0YjVlh84zBLJ1N+u1pcYhSsD+c5n0mICg3DF2E8ODYXulKSdmN6Y3VC z8oLGclapfsPYZulQ9xEDkvyrM/+rz0n9NBC0FmyztKRKg4MKu4jVOnXQ0SqYw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780652220; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4NVMRo8naU1n4HF6MKYBUtjyWxQw5YbxqDRQuQoeDpE=; b=1h5vRYP6Zn2PaLHJXX3SuoIF+3tdD1d4fyXoO/JCq3t77cDwPt0s/KifC6PHUQj6MYMD5r 0CF1RC0RKxpb6eDw== From: "tip-bot2 for Markus Stockhausen" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/irq-realtek-rtl: Add multicore support Cc: Markus Stockhausen , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260604182506.1113440-3-markus.stockhausen@gmx.de> References: <20260604182506.1113440-3-markus.stockhausen@gmx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178065221879.710.2323292721107647436.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: a1a35c09241f0577cc40f65d7372fed01138619d Gitweb: https://git.kernel.org/tip/a1a35c09241f0577cc40f65d7372fed01= 138619d Author: Markus Stockhausen AuthorDate: Thu, 04 Jun 2026 20:25:06 +02:00 Committer: Thomas Gleixner CommitterDate: Fri, 05 Jun 2026 11:35:10 +02:00 irqchip/irq-realtek-rtl: Add multicore support The Realtek interrupt driver currently supports only single core systems. So the higher end devices like RTL839x and RTL930x with dual VPEs must be driven with NR_CPU=3D1. Enhance the driver to support multicore (dual VPE) systems. For this: - Extend the register map for multiple cores - Search for multiple CPU cores in the devicetree - Improve the register helpers to support multiple cores - Add an affinity setter - Enhance the IRQ handler for multiple cores Signed-off-by: Markus Stockhausen Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260604182506.1113440-3-markus.stockhausen@= gmx.de --- drivers/irqchip/irq-realtek-rtl.c | 82 +++++++++++++++++++----------- 1 file changed, 54 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realte= k-rtl.c index f490fb8..2ae3be7 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -23,10 +23,10 @@ =20 #define RTL_ICTL_NUM_INPUTS 32 =20 -#define REG(x) (realtek_ictl_base + x) +#define REG(cpu, x) (realtek_ictl_base[cpu] + x) =20 static DEFINE_RAW_SPINLOCK(irq_lock); -static void __iomem *realtek_ictl_base; +static void __iomem *realtek_ictl_base[NR_CPUS]; =20 /* * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numberi= ng, @@ -37,27 +37,27 @@ static void __iomem *realtek_ictl_base; #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) #define IRR_SHIFT(idx) ((idx * 4) % 32) =20 -static inline void enable_gimr(unsigned int hw_irq) +static inline void enable_gimr(unsigned int cpu, unsigned int hw_irq) { u32 gimr; =20 - gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); gimr |=3D BIT(hw_irq); - writel(gimr, REG(RTL_ICTL_GIMR)); + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 -static inline void disable_gimr(unsigned int hw_irq) +static inline void disable_gimr(unsigned int cpu, unsigned int hw_irq) { u32 gimr; =20 - gimr =3D readl(REG(RTL_ICTL_GIMR)); + gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); gimr &=3D ~BIT(hw_irq); - writel(gimr, REG(RTL_ICTL_GIMR)); + writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 -static void write_irr(int hw_irq, u32 value) +static void write_irr(unsigned int cpu, int hw_irq, u32 value) { - void __iomem *irr0 =3D REG(RTL_ICTL_IRR0); + void __iomem *irr0 =3D REG(cpu, RTL_ICTL_IRR0); unsigned int offset =3D IRR_OFFSET(hw_irq); unsigned int shift =3D IRR_SHIFT(hw_irq); u32 irr; @@ -69,28 +69,51 @@ static void write_irr(int hw_irq, u32 value) =20 static void realtek_ictl_unmask_irq(struct irq_data *i) { + unsigned int cpu; + guard(raw_spinlock)(&irq_lock); - enable_gimr(i->hwirq); + for_each_cpu(cpu, irq_data_get_effective_affinity_mask(i)) + enable_gimr(cpu, i->hwirq); } =20 static void realtek_ictl_mask_irq(struct irq_data *i) { + unsigned int cpu; + guard(raw_spinlock)(&irq_lock); - disable_gimr(i->hwirq); + for_each_cpu(cpu, irq_data_get_effective_affinity_mask(i)) + disable_gimr(cpu, i->hwirq); +} + +static int realtek_ictl_irq_affinity(struct irq_data *i, const struct cpum= ask *dest, bool force) +{ + if (!irqd_irq_masked(i)) + realtek_ictl_mask_irq(i); + + irq_data_update_effective_affinity(i, dest); + + if (!irqd_irq_masked(i)) + realtek_ictl_unmask_irq(i); + + return IRQ_SET_MASK_OK; } =20 static struct irq_chip realtek_ictl_irq =3D { - .name =3D "realtek-rtl-intc", - .irq_mask =3D realtek_ictl_mask_irq, - .irq_unmask =3D realtek_ictl_unmask_irq, + .name =3D "realtek-rtl-intc", + .irq_mask =3D realtek_ictl_mask_irq, + .irq_unmask =3D realtek_ictl_unmask_irq, + .irq_set_affinity =3D realtek_ictl_irq_affinity, }; =20 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_= t hw) { + unsigned int cpu; + irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); =20 guard(raw_spinlock_irqsave)(&irq_lock); - write_irr(hw, 1); + for_each_present_cpu(cpu) + write_irr(cpu, hw, 1); =20 return 0; } @@ -103,12 +126,13 @@ static const struct irq_domain_ops irq_domain_ops =3D= { static void realtek_irq_dispatch(struct irq_desc *desc) { struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned int cpu =3D smp_processor_id(); struct irq_domain *domain; unsigned long pending; unsigned int soc_int; =20 chained_irq_enter(chip, desc); - pending =3D readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); + pending =3D readl(REG(cpu, RTL_ICTL_GIMR)) & readl(REG(cpu, RTL_ICTL_GISR= )); =20 if (unlikely(!pending)) { spurious_interrupt(); @@ -116,7 +140,7 @@ static void realtek_irq_dispatch(struct irq_desc *desc) } =20 domain =3D irq_desc_get_handler_data(desc); - for_each_set_bit(soc_int, &pending, 32) + for_each_set_bit(soc_int, &pending, RTL_ICTL_NUM_INPUTS) generic_handle_domain_irq(domain, soc_int); =20 out: @@ -127,16 +151,18 @@ static int __init realtek_rtl_of_init(struct device_n= ode *node, struct device_no { struct of_phandle_args oirq; struct irq_domain *domain; - int parent_irq; - - realtek_ictl_base =3D of_iomap(node, 0); - if (!realtek_ictl_base) - return -ENXIO; - - /* Disable all cascaded interrupts and clear routing */ - for (unsigned int hw_irq =3D 0; hw_irq < RTL_ICTL_NUM_INPUTS; hw_irq++) { - disable_gimr(hw_irq); - write_irr(hw_irq, 0); + int cpu, parent_irq; + + for_each_present_cpu(cpu) { + realtek_ictl_base[cpu] =3D of_iomap(node, cpu); + if (!realtek_ictl_base[cpu]) + return -ENXIO; + + /* Disable all cascaded interrupts and clear routing */ + for (unsigned int hw_irq =3D 0; hw_irq < RTL_ICTL_NUM_INPUTS; hw_irq++) { + disable_gimr(cpu, hw_irq); + write_irr(cpu, hw_irq, 0); + } } =20 if (WARN_ON(!of_irq_count(node))) {