From nobody Mon Jun 8 08:36:18 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88413425CD0; Wed, 3 Jun 2026 16:29:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504178; cv=none; b=rR7gQklxNrWocAN3r5kuu0xuw6YkwrLxr3xO2ZvCeJSk5wjfthdAqOccFrnMXpGbdYr1lrz33oPK+kfy8QKFBfnMjg3dldJy48fm/JhwcYXzJGz7plLGzKB1fINw+aD67zLgXGg7tARyShWEZKcL4XcikkNeHakEjp6fD2fuo3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504178; c=relaxed/simple; bh=bUK3rqorYAIqcu6Fr4mZmSGZGMJf1ECTBWsQmPuCq6Y=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=tWYpu5U6i3KK1J9aDNHP6vqB/pprwi9JbGFh63ixOXIbWbmMCW2D+EPAHKCmPYRzNklH3RxczQCSBG+IXns3+nKk/Mpip+54D1IfPyPmT+WqyEs3dz6oBdu0e4AeGh6uVCGolZFK2SoEXqwwIeEILB13pNFm36MWrpydHNs9SAs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ySgZatzo; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Cmw02g+Y; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ySgZatzo"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Cmw02g+Y" Date: Wed, 03 Jun 2026 16:29:30 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780504172; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dX7wFaYaiYGxMJYXggzgoSHTqoD3YSjVZBPA+QTlQa8=; b=ySgZatzowpSlLiV531XIxPQ4ZmeCWC+0zTpPURphAKp+4qRNXYpRx5qO8w8JIfjNmaQtlf jNA21GHrBfpav7o7o/X0SvFxlog/z8/FrlIm3oSYXFvdT/GEnC2eePJgErmdUsNnW31RUv vs9mF2Tc11nqzTEyIHLi6GhMV4311+HOUxj1J4BZz6ntqk2hz0l69Vlvg9OTiTSbBhazhE aQtumQAvuf9PYrbCjLROyWY2wYorM/s7bFQnoGVo4nzaFqECw3XJSvuGfAjG96CWCUOgkk ywWJfbHgRqKW5CZCCq1RI6tEjiRxAOkMYeCVvzuRwrDxu+aPHNVYJ0SajtNdkg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780504172; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dX7wFaYaiYGxMJYXggzgoSHTqoD3YSjVZBPA+QTlQa8=; b=Cmw02g+Yl3Z1rBMS74caWL6KSRSHGSmu+Y2yV08D8j6+sZXMxgckuNPpd8wbKkpNMtegE0 knT9JvNfwooRJQDw== From: "tip-bot2 for Cosmin Tanislav" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzt2h: Add software-triggered interrupts support Cc: Cosmin Tanislav , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260520203117.1516442-3-cosmin-gabriel.tanislav.xa@renesas.com> References: <20260520203117.1516442-3-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178050417037.710.11203046173131606805.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: a964dabc28a18fe62ff79e734cf54167ed322134 Gitweb: https://git.kernel.org/tip/a964dabc28a18fe62ff79e734cf54167e= d322134 Author: Cosmin Tanislav AuthorDate: Wed, 20 May 2026 23:31:16 +03:00 Committer: Thomas Gleixner CommitterDate: Wed, 03 Jun 2026 18:27:05 +02:00 irqchip/renesas-rzt2h: Add software-triggered interrupts support The Renesas RZ/T2H ICU supports software-triggerable interrupts. Add a dedicated rzt2h_icu_intcpu_chip irq_chip which implements rzt2h_icu_intcpu_set_irqchip_state() to allow injecting these interrupts. Request the INTCPU IRQs when IRQ injection is enabled to report them when they occur. Signed-off-by: Cosmin Tanislav Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260520203117.1516442-3-cosmin-gabriel.tani= slav.xa@renesas.com --- drivers/irqchip/irq-renesas-rzt2h.c | 123 ++++++++++++++++++++++++++- 1 file changed, 120 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-rene= sas-rzt2h.c index ecb69da..f7813d3 100644 --- a/drivers/irqchip/irq-renesas-rzt2h.c +++ b/drivers/irqchip/irq-renesas-rzt2h.c @@ -2,6 +2,7 @@ =20 #include #include +#include #include #include #include @@ -40,6 +41,9 @@ ((n) >=3D RZT2H_ICU_##type##_START && \ (n) < RZT2H_ICU_##type##_START + RZT2H_ICU_##type##_COUNT) =20 +#define RZT2H_ICU_SWINT 0x0 +#define RZT2H_ICU_SWINT_IC_MASK(i) BIT(i) + #define RZT2H_ICU_PORTNF_MD 0xc #define RZT2H_ICU_PORTNF_MDi_MASK(i) (GENMASK(1, 0) << ((i) * 2)) #define RZT2H_ICU_PORTNF_MDi_PREP(i, val) (FIELD_PREP(GENMASK(1, 0), val) = << ((i) * 2)) @@ -99,6 +103,12 @@ static inline int rzt2h_icu_irq_to_offset(struct irq_da= ta *d, void __iomem **bas } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_S) || RZT2H_ICU_IRQ_IN_RANGE= (hwirq, SEI)) { *offset =3D hwirq - RZT2H_ICU_IRQ_S_START; *base =3D priv->base_s; + } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_NS)) { + *offset =3D hwirq - RZT2H_ICU_INTCPU_NS_START; + *base =3D priv->base_ns; + } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_S)) { + *offset =3D hwirq - RZT2H_ICU_INTCPU_S_START; + *base =3D priv->base_s; } else { return -EINVAL; } @@ -164,6 +174,28 @@ static int rzt2h_icu_set_type(struct irq_data *d, unsi= gned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING); } =20 +static int rzt2h_icu_intcpu_set_irqchip_state(struct irq_data *d, enum irq= chip_irq_state which, + bool state) +{ + unsigned int offset; + void __iomem *base; + int ret; + + if (which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + ret =3D rzt2h_icu_irq_to_offset(d, &base, &offset); + if (ret) + return ret; + + writel_relaxed(RZT2H_ICU_SWINT_IC_MASK(offset), base + RZT2H_ICU_SWINT); + + return 0; +} + static const struct irq_chip rzt2h_icu_chip =3D { .name =3D "rzt2h-icu", .irq_mask =3D irq_chip_mask_parent, @@ -180,10 +212,27 @@ static const struct irq_chip rzt2h_icu_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzt2h_icu_intcpu_chip =3D { + .name =3D "rzt2h-icu", + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_wake =3D irq_chip_set_wake_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D rzt2h_icu_intcpu_set_irqchip_state, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static int rzt2h_icu_alloc(struct irq_domain *domain, unsigned int virq, u= nsigned int nr_irqs, void *arg) { struct rzt2h_icu_priv *priv =3D domain->host_data; + const struct irq_chip *chip; irq_hw_number_t hwirq; unsigned int type; int ret; @@ -192,7 +241,12 @@ static int rzt2h_icu_alloc(struct irq_domain *domain, = unsigned int virq, unsigne if (ret) return ret; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzt2h_icu_chi= p, NULL); + if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_NS) || RZT2H_ICU_IRQ_IN_RANGE(hw= irq, INTCPU_S)) + chip =3D &rzt2h_icu_intcpu_chip; + else + chip =3D &rzt2h_icu_chip; + + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, NULL); if (ret) return ret; =20 @@ -222,6 +276,60 @@ static int rzt2h_icu_parse_interrupts(struct rzt2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzt2h_icu_intcpu_irq(int irq, void *data) +{ + unsigned int intcpu =3D (uintptr_t)data; + + pr_info("INTCPU%u software interrupt\n", intcpu); + return IRQ_HANDLED; +} + +static int rzt2h_icu_request_irqs(struct platform_device *pdev, struct irq= _domain *irq_domain, + unsigned int start, unsigned int count, irq_handler_t handler, + void *data) +{ + struct device *dev =3D &pdev->dev; + unsigned int offset, virq; + struct irq_fwspec fwspec; + int ret; + + for (offset =3D start; offset < start + count; offset++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D offset; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) + return dev_err_probe(dev, -EINVAL, "Failed to create IRQ %u mapping\n",= offset); + + ret =3D devm_request_irq(dev, virq, handler, 0, dev_name(dev), + data ?: (void *)(uintptr_t)offset); + if (ret) + return dev_err_probe(dev, ret, "Failed to request IRQ %u\n", offset); + } + + return 0; +} + +static int rzt2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) +{ + if (IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION)) { + int ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_NS= _START, + RZT2H_ICU_INTCPU_NS_COUNT, rzt2h_icu_intcpu_irq, + NULL); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_S_STAR= T, + RZT2H_ICU_INTCPU_S_COUNT, rzt2h_icu_intcpu_irq, NULL); + if (ret) + return ret; + } + + return 0; +} + static int rzt2h_icu_init(struct platform_device *pdev, struct device_node= *parent) { struct irq_domain *irq_domain, *parent_domain; @@ -265,11 +373,20 @@ static int rzt2h_icu_init(struct platform_device *pde= v, struct device_node *pare irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NU= M_IRQ, dev_fwnode(dev), &rzt2h_icu_domain_ops, priv); if (!irq_domain) { - pm_runtime_put_sync(dev); - return -ENOMEM; + ret =3D -ENOMEM; + goto err_pm_put; } =20 + ret =3D rzt2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto err_irq_domain_free; return 0; + +err_irq_domain_free: + irq_domain_remove(irq_domain); +err_pm_put: + pm_runtime_put_sync(dev); + return ret; } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzt2h_icu)