From nobody Mon Jun 8 08:30:20 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35A923ED3B9; Wed, 3 Jun 2026 16:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504176; cv=none; b=gNqVTffa5+RewI3Z/oWQJ6EcyGGJLRHj5KiDfTTLgebzeVvIA1/O759YO+TAUHjUMZnEg6Dj3YLYT9z6Pgo9cDMHIT0cLGQWTnMoyo3ggxpaJCMU/EXXK1hUbTKmVbYsdxwZUsZ0e/VaY53zVs/NrvnczYuNfgQa1/hNHHtErTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504176; c=relaxed/simple; bh=y9aIaMdWKQiaCyvU+Sgeuq+tgyT1eqN+RweMUmw8Ijw=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=aghDgR+2LCEKySM32NQzfMRhSOLhB1/4nPIXeaJ3Ab+9ph3i+1cjSdSFOzIrP8ND2oLNNscYDLPZUzPgpyMJAfyk3qkSkk4pwfRPaHmP9zkoy0Iq8ZHHOD4EOzHSJpDCAntQv4sun/DgPfA6fsFsnQSOo0tworh5vOk0uqqHiww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ApkUn3wU; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=22En5Ohb; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ApkUn3wU"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="22En5Ohb" Date: Wed, 03 Jun 2026 16:29:28 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780504170; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rd9sLSnPIMLMwxXOUZTmQIUK2YmDVCOHXMHoriVRnEw=; b=ApkUn3wUU7ANFR1pmaiUmJpLY2XV9z89MYsfno1ZEgHKoVC8cdD2BuBqn/dHwNhSgRF9uo 4mb1CNV9C/8LS9VlkmsW3i+N+/hZj/4nbRpLTeYaEimC+lAGvzPqfufkYdM9h0knGjunLK zOWoFkXY5iTfUwJIY2R7ONuqpV6wP9/MGRocNu+XbzWPgahxodQNrYSAvPyShrUAdrrdxP rXLck1Lgxk7PKuwNtv+VpHOPgZlcIuuZ0FCcgTpQqImjM4Y4gOtmY8FfXMFwnFbuGfPDOM umAnxBHyDG2uOFPYfaMZc1uqZY8WFokPTv9TdIYksI5RssReAIYzY5Nk5SV18g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780504170; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rd9sLSnPIMLMwxXOUZTmQIUK2YmDVCOHXMHoriVRnEw=; b=22En5OhbzLmTzxo0+qEh5MwOdg95mMt5gEMXT+Z9eAXw04qD0UjLq1j0YysowU2dFAWKSq 2f/xkcXdxQf+iXAg== From: "tip-bot2 for Cosmin Tanislav" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/renesas-rzt2h: Add error interrupts support Cc: Cosmin Tanislav , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260520203117.1516442-4-cosmin-gabriel.tanislav.xa@renesas.com> References: <20260520203117.1516442-4-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178050416894.710.17529786016845294285.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 8d721c08dd67af96664ce381f6b2790d15de7213 Gitweb: https://git.kernel.org/tip/8d721c08dd67af96664ce381f6b2790d1= 5de7213 Author: Cosmin Tanislav AuthorDate: Wed, 20 May 2026 23:31:17 +03:00 Committer: Thomas Gleixner CommitterDate: Wed, 03 Jun 2026 18:27:05 +02:00 irqchip/renesas-rzt2h: Add error interrupts support The Renesas RZ/T2H ICU is able to report errors for CA55, GIC, and various IPs. Unmask these errors, request the IRQs and report them when they occur. Signed-off-by: Cosmin Tanislav Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260520203117.1516442-4-cosmin-gabriel.tani= slav.xa@renesas.com --- drivers/irqchip/irq-renesas-rzt2h.c | 151 ++++++++++++++++++++++++++- 1 file changed, 147 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-rene= sas-rzt2h.c index f7813d3..e06264a 100644 --- a/drivers/irqchip/irq-renesas-rzt2h.c +++ b/drivers/irqchip/irq-renesas-rzt2h.c @@ -31,11 +31,36 @@ RZT2H_ICU_IRQ_S_COUNT) #define RZT2H_ICU_SEI_COUNT 1 =20 +#define RZT2H_ICU_CA55_ERR_START (RZT2H_ICU_SEI_START + \ + RZT2H_ICU_SEI_COUNT) +#define RZT2H_ICU_CA55_ERR_COUNT 2 + +#define RZT2H_ICU_CR52_ERR_START (RZT2H_ICU_CA55_ERR_START + \ + RZT2H_ICU_CA55_ERR_COUNT) +#define RZT2H_ICU_CR52_ERR_COUNT 4 + +#define RZT2H_ICU_PERI_ERR_START (RZT2H_ICU_CR52_ERR_START + \ + RZT2H_ICU_CR52_ERR_COUNT) +#define RZT2H_ICU_PERI_ERR_COUNT 2 + +#define RZT2H_ICU_DSMIF_ERR_START (RZT2H_ICU_PERI_ERR_START + \ + RZT2H_ICU_PERI_ERR_COUNT) +#define RZT2H_ICU_DSMIF_ERR_COUNT 2 + +#define RZT2H_ICU_ENCIF_ERR_START (RZT2H_ICU_DSMIF_ERR_START + \ + RZT2H_ICU_DSMIF_ERR_COUNT) +#define RZT2H_ICU_ENCIF_ERR_COUNT 2 + #define RZT2H_ICU_NUM_IRQ (RZT2H_ICU_INTCPU_NS_COUNT + \ RZT2H_ICU_INTCPU_S_COUNT + \ RZT2H_ICU_IRQ_NS_COUNT + \ RZT2H_ICU_IRQ_S_COUNT + \ - RZT2H_ICU_SEI_COUNT) + RZT2H_ICU_SEI_COUNT + \ + RZT2H_ICU_CA55_ERR_COUNT + \ + RZT2H_ICU_CR52_ERR_COUNT + \ + RZT2H_ICU_PERI_ERR_COUNT + \ + RZT2H_ICU_DSMIF_ERR_COUNT + \ + RZT2H_ICU_ENCIF_ERR_COUNT) =20 #define RZT2H_ICU_IRQ_IN_RANGE(n, type) \ ((n) >=3D RZT2H_ICU_##type##_START && \ @@ -53,6 +78,29 @@ #define RZT2H_ICU_MD_RISING_EDGE 0b10 #define RZT2H_ICU_MD_BOTH_EDGES 0b11 =20 +#define RZT2H_ICU_CA55ERR_E0MSK 0x50 +#define RZT2H_ICU_CA55ERR_CLR 0x60 +#define RZT2H_ICU_CA55ERR_STAT 0x64 +#define RZT2H_ICU_CA55ERR_MASK GENMASK(12, 0) + +#define RZT2H_ICU_PERIERR_E0MSKn(n) (0x98 + 0x4 * (n)) +#define RZT2H_ICU_PERIERR_CLRn(n) (0xc8 + 0x4 * (n)) +#define RZT2H_ICU_PERIERR_STAT 0xd4 +#define RZT2H_ICU_PERIERR_NUM 3 +#define RZT2H_ICU_PERIERR_MASK GENMASK(31, 0) + +#define RZT2H_ICU_DSMIFERR_E0MSKn(n) (0xe0 + 0x4 * (n)) +#define RZT2H_ICU_DSMIFERR_CLRn(n) (0x1a0 + 0x4 * (n)) +#define RZT2H_ICU_DSMIFERR_STAT 0x1d0 +#define RZT2H_ICU_DSMIFERR_NUM 12 +#define RZT2H_ICU_DSMIFERR_MASK GENMASK(31, 0) + +#define RZT2H_ICU_ENCIFERR_E0MSKn(n) (0x200 + 0x4 * (n)) +#define RZT2H_ICU_ENCIFERR_CLRn(n) (0x250 + 0x4 * (n)) +#define RZT2H_ICU_ENCIFERR_STAT 0x264 +#define RZT2H_ICU_ENCIFERR_NUM 5 +#define RZT2H_ICU_ENCIFERR_MASK GENMASK(31, 0) + #define RZT2H_ICU_DMACn_RSSELi(n, i) (0x7d0 + 0x18 * (n) + 0x4 * (i)) #define RZT2H_ICU_DMAC_REQ_SELx_MASK(x) (GENMASK(9, 0) << ((x) * 10)) #define RZT2H_ICU_DMAC_REQ_SELx_PREP(x, val) (FIELD_PREP(GENMASK(9, 0), va= l) << ((x) * 10)) @@ -284,6 +332,50 @@ static irqreturn_t rzt2h_icu_intcpu_irq(int irq, void = *data) return IRQ_HANDLED; } =20 +static irqreturn_t rzt2h_icu_err_irq(struct rzt2h_icu_priv *priv, const ch= ar *name, + unsigned int num, u32 stat_base, u32 clr_base) +{ + bool handled =3D false; + + for (unsigned int n =3D 0; n < num; n++) { + u32 stat =3D readl(priv->base_ns + stat_base + n * 0x4); + + if (!stat) + continue; + + handled =3D true; + + pr_err("rzt2h-icu: %s error n=3D%u status=3D0x%08x\n", name, n, stat); + + writel_relaxed(stat, priv->base_ns + clr_base + n * 0x4); + } + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static irqreturn_t rzt2h_icu_ca55_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "CA55", 1, RZT2H_ICU_CA55ERR_STAT, RZT2H_I= CU_CA55ERR_CLR); +} + +static irqreturn_t rzt2h_icu_peri_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "peripheral", RZT2H_ICU_PERIERR_NUM, RZT2H= _ICU_PERIERR_STAT, + RZT2H_ICU_PERIERR_CLRn(0)); +} + +static irqreturn_t rzt2h_icu_dsmif_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "DSMIF", RZT2H_ICU_DSMIFERR_NUM, RZT2H_ICU= _DSMIFERR_STAT, + RZT2H_ICU_DSMIFERR_CLRn(0)); +} + +static irqreturn_t rzt2h_icu_encif_err_irq(int irq, void *data) +{ + return rzt2h_icu_err_irq(data, "ENCIF", RZT2H_ICU_ENCIFERR_NUM, RZT2H_ICU= _ENCIFERR_STAT, + RZT2H_ICU_ENCIFERR_CLRn(0)); +} + static int rzt2h_icu_request_irqs(struct platform_device *pdev, struct irq= _domain *irq_domain, unsigned int start, unsigned int count, irq_handler_t handler, void *data) @@ -314,10 +406,13 @@ static int rzt2h_icu_request_irqs(struct platform_dev= ice *pdev, struct irq_domai =20 static int rzt2h_icu_setup_irqs(struct platform_device *pdev, struct irq_d= omain *irq_domain) { + struct rzt2h_icu_priv *priv =3D platform_get_drvdata(pdev); + unsigned int n; + int ret; + if (IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION)) { - int ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_NS= _START, - RZT2H_ICU_INTCPU_NS_COUNT, rzt2h_icu_intcpu_irq, - NULL); + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_NS_STA= RT, + RZT2H_ICU_INTCPU_NS_COUNT, rzt2h_icu_intcpu_irq, NULL); if (ret) return ret; =20 @@ -327,6 +422,54 @@ static int rzt2h_icu_setup_irqs(struct platform_device= *pdev, struct irq_domain=20 return ret; } =20 + /* + * There are two error interrupts and two error masks that can be used + * separately for each error type. It would not be very useful to + * receive two interrupts for the same error, so use only the first one. + */ + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_CA55_ERR_START= , 1, + rzt2h_icu_ca55_err_irq, priv); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_PERI_ERR_START= , 1, + rzt2h_icu_peri_err_irq, priv); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_DSMIF_ERR_STAR= T, 1, + rzt2h_icu_dsmif_err_irq, priv); + if (ret) + return ret; + + ret =3D rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_ENCIF_ERR_STAR= T, 1, + rzt2h_icu_encif_err_irq, priv); + if (ret) + return ret; + + /* Clear and unmask CA55 error events */ + writel_relaxed(RZT2H_ICU_CA55ERR_MASK, priv->base_ns + RZT2H_ICU_CA55ERR_= CLR); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_CA55ERR_E0MSK); + + /* Clear and unmask peripheral error events */ + for (n =3D 0; n < RZT2H_ICU_PERIERR_NUM; n++) { + writel_relaxed(RZT2H_ICU_PERIERR_MASK, priv->base_ns + RZT2H_ICU_PERIERR= _CLRn(n)); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_PERIERR_E0MSKn(n)); + } + + /* Clear and unmask DSMIF error events */ + for (n =3D 0; n < RZT2H_ICU_DSMIFERR_NUM; n++) { + writel_relaxed(RZT2H_ICU_DSMIFERR_MASK, priv->base_ns + RZT2H_ICU_DSMIFE= RR_CLRn(n)); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_DSMIFERR_E0MSKn(n)); + } + + /* Clear and unmask ENCIF error events */ + for (n =3D 0; n < RZT2H_ICU_ENCIFERR_NUM; n++) { + writel_relaxed(RZT2H_ICU_ENCIFERR_MASK, priv->base_ns + RZT2H_ICU_ENCIFE= RR_CLRn(n)); + writel_relaxed(0, priv->base_ns + RZT2H_ICU_ENCIFERR_E0MSKn(n)); + } + return 0; } =20