From nobody Mon Jun 8 08:52:46 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B252F3F44E4; Wed, 3 Jun 2026 16:29:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504173; cv=none; b=OaohMHAEUHU5NTWgodx7crKwTu2cf56kscfDUyRajPZQK/2qtEc5pxZdJ+hA//ImA9xKi9JQM9ixvtAcV9o3vpWdlTcgwppBJGJeE/kvTF8o0Kuf6Ys5Q+EUohhUYyDITEyOfadMKkF0CTL5Y92hBRto652j2AsiTkLJ8PAmMIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504173; c=relaxed/simple; bh=fMgIqz2HQ+o8GP9rVQ1aVpZmKxGScs8G1I0OPbYBmUw=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=M4MFXy7FWpBU0ocydJonL6Xr2hwMRpwKjUwCf5cmzcUqIcLkd0vV7stKPcwYA5a9iXVuA2vKNf5hIMufDxGQMlhevNLBC/mxhep3neU3fmLHq6pssXYLTFaUkROeYOqU+TAkYprY5e43TQ3mm7OOo5xY+ABepnZyHTzi+JPuid4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=44p0Iqik; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rSTNuqzZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="44p0Iqik"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rSTNuqzZ" Date: Wed, 03 Jun 2026 16:29:26 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780504167; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=40u+5DpdWjYrWF5dPFCo2rV4wwlJxRXxp15wGHDSBlU=; b=44p0Iqik6Us2cL7uYwo6oDbWW6gSnj25nK3sEQUt2EfsDeMuylOGGRYoQZKnxWEiHiRkE+ nn9o1a9MAVQdN5CGHVwoCyWk3aag8RK06pz1HTfOt06RGE7UYpJhet5Cj0ukNrJpAxmNnk e5tuxXoXvTN6ot1jqsPvwZyVxikQXpK63pJjqck9FfR5R9u5kiZfEbYbACWHoDgUEa/IHu PudyQZj80Z1D9JL8XF6JjM896xPAJ1CZC5U+Q8FQc4pi/ChIhlPCL2us3GrjJOL71of0AT Y4CPnm88jtnA2F9zHJm9bxBqWsdu4qriiDEv0/Ld9wzj/TP0mGO9J610XcYKBQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780504167; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=40u+5DpdWjYrWF5dPFCo2rV4wwlJxRXxp15wGHDSBlU=; b=rSTNuqzZb3ruRm3Veky1/rEGFr2sUsa8Rc6tP5B12J9b5h1WO8A+3g0SDqIjHCtcIPAtkk AJYpCqaT/25AruBA== From: "tip-bot2 for Mukesh Ojha" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers Cc: Mukesh Ojha , Thomas Gleixner , Dmitry Baryshkov , Konrad Dybcio , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260527095426.2324504-2-mukesh.ojha@oss.qualcomm.com> References: <20260527095426.2324504-2-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178050416618.710.7810926365439435212.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 668f3382845b3751220c6fcdd4c4cda0c2f0c78f Gitweb: https://git.kernel.org/tip/668f3382845b3751220c6fcdd4c4cda0c= 2f0c78f Author: Mukesh Ojha AuthorDate: Wed, 27 May 2026 15:24:23 +05:30 Committer: Thomas Gleixner CommitterDate: Wed, 03 Jun 2026 18:27:05 +02:00 irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers The __pdc_enable_intr() function contains a version branch that selects between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for HW >=3D 3.2. These two paths share no code and serve different hardware. Split them into two focused static functions: pdc_enable_intr_bank() for HW < 3.2 and pdc_enable_intr_cfg() for HW >=3D 3.2. No functional change. Signed-off-by: Mukesh Ojha Signed-off-by: Thomas Gleixner Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260527095426.2324504-2-mukesh.ojha@oss.qua= lcomm.com --- drivers/irqchip/qcom-pdc.c | 41 ++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 32b77fa..5f0da15 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -97,28 +97,37 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enab= le) pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable); } =20 -static void __pdc_enable_intr(int pin_out, bool on) +static void pdc_enable_intr_bank(int pin_out, bool on) { unsigned long enable; + u32 index, mask; =20 - if (pdc_version < PDC_VERSION_3_2) { - u32 index, mask; + index =3D pin_out / 32; + mask =3D pin_out % 32; =20 - index =3D pin_out / 32; - mask =3D pin_out % 32; + enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); + __assign_bit(mask, &enable, on); =20 - enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); - __assign_bit(mask, &enable, on); + if (pdc_x1e_quirk) + pdc_x1e_irq_enable_write(index, enable); + else + pdc_reg_write(IRQ_ENABLE_BANK, index, enable); +} =20 - if (pdc_x1e_quirk) - pdc_x1e_irq_enable_write(index, enable); - else - pdc_reg_write(IRQ_ENABLE_BANK, index, enable); - } else { - enable =3D pdc_reg_read(IRQ_i_CFG, pin_out); - __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); - pdc_reg_write(IRQ_i_CFG, pin_out, enable); - } +static void pdc_enable_intr_cfg(int pin_out, bool on) +{ + unsigned long enable =3D pdc_reg_read(IRQ_i_CFG, pin_out); + + __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); + pdc_reg_write(IRQ_i_CFG, pin_out, enable); +} + +static void __pdc_enable_intr(int pin_out, bool on) +{ + if (pdc_version < PDC_VERSION_3_2) + pdc_enable_intr_bank(pin_out, on); + else + pdc_enable_intr_cfg(pin_out, on); } =20 static void pdc_enable_intr(struct irq_data *d, bool on)