From nobody Mon Jun 8 08:30:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0A193E9595; Wed, 3 Jun 2026 16:29:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504169; cv=none; b=lXyqE0P4k8CIEfX2I3YPzxfFcSXcYg+H1q0fMLkr5UYAybxJbxFMFTRV41Rky2YWvwPlWXPaqtjWn2UDSp42w7j1GLwDYnAbCfInYU9pDjDycQfaIiLTUZkrCQhyfP5PilJG/k2LYZP/pHARkzbjXVp8/pPvKrGfB/wX87sXNX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504169; c=relaxed/simple; bh=TPPgJPXEJwSPBaoinQjiGVv/fI/ffu1XCIWiuDU24xE=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=TI3ZKyzg8VBFQvPIpw8AGcZjl4782X/Blo74cBkfFpsGCdJMwbj9pIIm0e36fAzH2QFt90VyNwbNhD3xUTSxWuwJaBFM6Q4kIQwRScm856Y2hg+DeG59j1ubF0Hi77/ooCk6bB5zCK+5p14KRTPz3hxBvngYthsXaIz0bMjR4d8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zWbiK7ZR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JPoYFmL8; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zWbiK7ZR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JPoYFmL8" Date: Wed, 03 Jun 2026 16:29:23 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780504164; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I1TH5KS1ZOvpx0Pb/c3xpAzAXzZh8azTM2LiObnhs+g=; b=zWbiK7ZRRXX89LUY8uNASwsuCzCeKgrtJVmCZZMU9EskwEiYY6/kKa4uXvCqKZ59VUj/ox bqPKsMwhH9U0HwtQVEvqjuk5dhwgJr+cmubpycpWhInoXH1XHWLYdZ88Iz8TfwT8prcBpn oYT9qA7wQxYOXVuvMsAhI/zoS3CWr/i+qGjPm4a9jPWkXVIzAG64bHV86kEQXGNgegwks3 tuNd9bjvDBji5O/yO4YL+epCT2tlu4jVS4/xLNAP78426NOlbQj/ZbwwyziAG3PhRzP97o uwz47hJk0S6oi6E5u1LEXyOYTVrGHJ0vQR5hbxOuquFchCKcpsomilm3mNhpaA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780504164; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I1TH5KS1ZOvpx0Pb/c3xpAzAXzZh8azTM2LiObnhs+g=; b=JPoYFmL8JTbCEqHIEOILsZDgzM9oUg0i5zNqsIpxxtnhX12U4WpbxdFCGJKUIm5y3cym1p 7YuGob6xyFRuLsCg== From: "tip-bot2 for Mukesh Ojha" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/qcom-pdc: Add PDC_VERSION() macro to describe version register fields Cc: Mukesh Ojha , Thomas Gleixner , Dmitry Baryshkov , Konrad Dybcio , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260527095426.2324504-4-mukesh.ojha@oss.qualcomm.com> References: <20260527095426.2324504-4-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178050416341.710.17637928410250212224.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: ef631c422f2cc3f5a8c0687364bfafec4f3d531c Gitweb: https://git.kernel.org/tip/ef631c422f2cc3f5a8c0687364bfafec4= f3d531c Author: Mukesh Ojha AuthorDate: Wed, 27 May 2026 15:24:25 +05:30 Committer: Thomas Gleixner CommitterDate: Wed, 03 Jun 2026 18:27:05 +02:00 irqchip/qcom-pdc: Add PDC_VERSION() macro to describe version register fiel= ds The PDC hardware version register encodes major, minor and step fields in byte-sized fields at bits [23:16], [15:8] and [7:0] respectively. The existing PDC_VERSION_3_2 constant was a bare magic number (0x30200) with no indication of this encoding. Add GENMASK-based field definitions for each sub-field and a PDC_VERSION(maj, min, step) constructor macro using FIELD_PREP, making the encoding self-documenting. Replace the magic constant with PDC_VERSION(3, 2, 0). Signed-off-by: Mukesh Ojha Signed-off-by: Thomas Gleixner Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260527095426.2324504-4-mukesh.ojha@oss.qua= lcomm.com --- drivers/irqchip/qcom-pdc.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 0b82306..08eec00 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -3,6 +3,7 @@ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ =20 +#include #include #include #include @@ -31,12 +32,18 @@ /* Valid only on HW version >=3D 3.2 */ #define IRQ_i_CFG_IRQ_ENABLE 3 =20 -#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) +#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) =20 -#define PDC_VERSION_REG 0x1000 +#define PDC_VERSION_REG 0x1000 +#define PDC_VERSION_MAJOR GENMASK(23, 16) +#define PDC_VERSION_MINOR GENMASK(15, 8) +#define PDC_VERSION_STEP GENMASK(7, 0) +#define PDC_VERSION(maj, min, step) (FIELD_PREP(PDC_VERSION_MAJOR, (maj)) = | \ + FIELD_PREP(PDC_VERSION_MINOR, (min)) | \ + FIELD_PREP(PDC_VERSION_STEP, (step))) =20 /* Notable PDC versions */ -#define PDC_VERSION_3_2 0x30200 +#define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0) =20 struct pdc_pin_region { u32 pin_base;