From nobody Mon Jun 8 08:30:33 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F097E3E2756; Wed, 3 Jun 2026 16:29:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504168; cv=none; b=ELitjvzOtiem/0Vuj+O58g4Osb8+/KcNYl48J5bIj+MAAg57ZFd4/1iWMEqkT4YvBktiU0B5GL478fENUwcQncVrT3rHOAdMKWvKezPeMrRNgvR5O0RT5dAPdP74wpYuseOeqIooBGOC60ub7MRADQ8nQwFIIdwh5FCTFezhmpU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780504168; c=relaxed/simple; bh=HDdKnW1dg7uylw6CgEsqlha6R32DNFme6SAfolFpggM=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Owb05xckOC5cWQ1OkLfKiCtqTZamMcJ5htxE4w6vrV2UtEgoI/HJNIkaOu+xc+AvJQEICmolE8Gt2sCcHojEvuwUizc6o27VJ6EciMTZltdjcG4J2umpDTOQLlS8zHyHNZ3U5HORiAnBJRXMqb2KSjcM+RYT17GxnQyJoFXpjwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PJb2CEb+; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ETKRr2s5; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PJb2CEb+"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ETKRr2s5" Date: Wed, 03 Jun 2026 16:29:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780504163; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GBhpBCCPEITQZ6n8otU3xAL6QpCgOK044YXKOAdJOIk=; b=PJb2CEb+Yt5ySKNjlPU1o5/albiw/g02LwPv2jfBOTz6CTcD+y3NXNcHrDKK0MgULraNFq hbyn0VkX7/B2JD4l4HXQg3sxxvciduD82hHmFMya3wRhkzPot7fLjrsomfVjm8DLVVsXLr v0ZfW2l5uVb08Z3EBUx9FLl0s4MZ8XwHojMl4ib+OGBA/NBWS73F4Cc0wh0V4dxf8i59hl o/wB2PmwlRogdsoAb49oT3Tw+v8G/T+SQdxIT94iBEn+KR6qD4tVW67wko/Q6Oce9oQF/b tzwJelo5XYjK96vmOqmjzlRgCxmj9XTw5W/nOs1CwE0AHyuAasvOCWs+R5cAeA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780504163; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GBhpBCCPEITQZ6n8otU3xAL6QpCgOK044YXKOAdJOIk=; b=ETKRr2s5q7WQafOELix+dhyL3+9MdKJsOY6jSfyOgMjA5+RRffzSJ/3YWQNRpH3F86ajvm lSED3muPfo0IkTBQ== From: "tip-bot2 for Mukesh Ojha" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit position Cc: Mukesh Ojha , Thomas Gleixner , Konrad Dybcio , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260527095426.2324504-5-mukesh.ojha@oss.qualcomm.com> References: <20260527095426.2324504-5-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178050416209.710.13233344380148714274.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 8766c87e9bb499b5e2b04b9f51f9e525d41c5b46 Gitweb: https://git.kernel.org/tip/8766c87e9bb499b5e2b04b9f51f9e525d= 41c5b46 Author: Mukesh Ojha AuthorDate: Wed, 27 May 2026 15:24:26 +05:30 Committer: Thomas Gleixner CommitterDate: Wed, 03 Jun 2026 18:27:06 +02:00 irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit position The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit represents one PDC pin. The bank index and bit position within the bank are encoded in the flat pin number as bits [31:5] and [4:0] respectively. Replace the open-coded division and modulo with FIELD_GET() and GENMASK() to make the bit extraction self-documenting and consistent with the FIELD_PREP() style already used in the PDC_VERSION() macro. Signed-off-by: Mukesh Ojha Signed-off-by: Thomas Gleixner Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260527095426.2324504-5-mukesh.ojha@oss.qua= lcomm.com --- drivers/irqchip/qcom-pdc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 08eec00..2014dbb 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -27,6 +27,8 @@ /* Valid only on HW version < 3.2 */ #define IRQ_ENABLE_BANK 0x10 #define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_= IRQS)) +#define IRQ_ENABLE_BANK_INDEX_MASK GENMASK(31, 5) +#define IRQ_ENABLE_BANK_BIT_MASK GENMASK(4, 0) #define IRQ_i_CFG 0x110 =20 /* Valid only on HW version >=3D 3.2 */ @@ -109,8 +111,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on) unsigned long enable; u32 index, mask; =20 - index =3D pin_out / 32; - mask =3D pin_out % 32; + index =3D FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out); + mask =3D FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out); =20 enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); __assign_bit(mask, &enable, on);