From nobody Mon Jun 8 08:47:31 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8D31481FAF; Wed, 3 Jun 2026 14:25:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780496704; cv=none; b=QUAJKwLbzBO678TQrx7uKk+8BCZvC5Gx049/pPATbqFe0q6Pqk/brqVp/l5UlX84hdGgn2sM9Ed3jkqCATSDvZ7qdf0FNIddZY0CzFOryNmZzVYM4qb9102AKYKp1Dd5I9dO0u0SV+bQ70HkJiLcctzHV24qiOotNKnCiU40IXo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780496704; c=relaxed/simple; bh=s2UWX8+vxgOaaTFQUxDoj4EjYnhrE90z2P6DMolsDhA=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=tQ86v7hre2eLmgGqJLUAl7vullBdqYo28d3q9VoCJinhI3j4ek786ZHMqAVV0w9IVl7VM9gN5JmeNhvVXjrIGcB96Jc43EmHun1gEgHzp9F5WbAp9IGMwM3xntpc101e2l8m6g2AGtnso8EHBeuJSzxzW28x3P1t63duKoEDOBE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CYJJzxIv; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ywEkj6Fb; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CYJJzxIv"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ywEkj6Fb" Date: Wed, 03 Jun 2026 14:24:59 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780496701; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PpvOpjp9hQdse4mOGFbo3ve2QofmNeIhWg8xAaPM1hg=; b=CYJJzxIvCEy1Pe0e4fdGelxGPjCnOifq5pU+Dww8NZoCA9tU3ivbIShkfUUorGx3P8Eojd 7+cf66Bk0tWaoTFWNCmyQni6TQTb7iMnqoCtDUwU1UxzgfJMLFSDkyqHvWFIWTROqC71xX RJL3fFgDlZd2pptLaQ6H+GlrsDYOCYEeKsDfjl355wmCIjt1zYTP7p1MPBGObC4oiUkTP9 VEhEBghfN06OafL0W+3NbVp6HXwgOtlKIlL53zrda1PH/wYWAVvISyCTbG0vDJFn228567 Y4xHhONITF4eq2Btz5sM8LMCXm/EenCUeDMe38hafeWMj6YD8e7r0EtACZMsoQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780496701; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PpvOpjp9hQdse4mOGFbo3ve2QofmNeIhWg8xAaPM1hg=; b=ywEkj6Fb983yST3xJJOhUIRj3eaaJLBSqPztE27yH367W5S0kC1fDJj8i06qp6ba4zmhpO 7LuveDrzwO660EDg== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] uaccess: Provide unsafe_atomic_store_release_user() Cc: Thomas Gleixner , "Peter Zijlstra (Intel)" , andrealmeid@igalia.com, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260602090535.513181528@kernel.org> References: <20260602090535.513181528@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178049669993.710.16750845848504294626.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: 6149fc36c09b91050b62e8e68a91027df8df7345 Gitweb: https://git.kernel.org/tip/6149fc36c09b91050b62e8e68a91027df= 8df7345 Author: Thomas Gleixner AuthorDate: Tue, 02 Jun 2026 11:09:42 +02:00 Committer: Peter Zijlstra CommitterDate: Wed, 03 Jun 2026 11:38:50 +02:00 uaccess: Provide unsafe_atomic_store_release_user() The upcoming support for unlocking robust futexes in the kernel requires store release semantics. Syscalls do not imply memory ordering on all architectures so the unlock operation requires a barrier. This barrier can be avoided when stores imply release like on x86. Provide a generic version with a smp_mb() before the unsafe_put_user(), which can be overridden by architectures. Provide also a ARCH_MEMORY_ORDER_TSO Kconfig option, which can be selected by architectures with Total Store Order (TSO), where store implies release, so that the smp_mb() in the generic implementation can be avoided. If that is set a barrier() is used instead of smp_mb(), which is not required for the use case at hand, but makes it future proof for other usage to prevent the compiler from reordering. Signed-off-by: Thomas Gleixner Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Andr=C3=A9 Almeida Link: https://patch.msgid.link/20260602090535.513181528@kernel.org --- arch/Kconfig | 4 ++++ include/linux/uaccess.h | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/Kconfig b/arch/Kconfig index e868800..83d362f 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -403,6 +403,10 @@ config ARCH_32BIT_OFF_T config ARCH_32BIT_USTAT_F_TINODE bool =20 +# Selected by architectures with Total Store Order (TSO) +config ARCH_MEMORY_ORDER_TSO + bool + config HAVE_ASM_MODVERSIONS bool help diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index 5632860..c6bd200 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -649,6 +649,17 @@ static inline void user_access_restore(unsigned long f= lags) { } #define user_read_access_end user_access_end #endif =20 +#ifndef unsafe_atomic_store_release_user +# define unsafe_atomic_store_release_user(val, uptr, elbl) \ + do { \ + if (!IS_ENABLED(CONFIG_ARCH_MEMORY_ORDER_TSO)) \ + smp_mb(); \ + else \ + barrier(); \ + unsafe_put_user(val, uptr, elbl); \ + } while (0) +#endif + /* Define RW variant so the below _mode macro expansion works */ #define masked_user_rw_access_begin(u) masked_user_access_begin(u) #define user_rw_access_begin(u, s) user_access_begin(u, s)