From nobody Mon Jun 8 08:30:34 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B234481FA8; Wed, 3 Jun 2026 14:25:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780496703; cv=none; b=EYcrN2PJ50WbRBrJX1mmigJSHzOxFdCFCFOgRVUgHFiQXNU3ExsWyYVeO6XP1L+pXSKf2rw8Cgz0w2GCglacoh8zpZKjbYeoD8uRE2Q4tgsR0uSPaTrXPtRa0E40NaGDucmmM7azgWEM1DZyBFHtAVsX86NLpv0Z8feqEZqQDCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780496703; c=relaxed/simple; bh=a3o2N7yKghfbV2LYyTKNKA/OGT894rah0JUYZS7pjko=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=V1w6xu7SbtmvuRXiqlfVY0m4lgGJVyi5akfCQods6Rf8iJmaE/x1zq0KBTGBEXxBM7z6f1m8T0Pmd3XK3hcY8stfAJoOOkONYKO97cPipF9MWumrn/ZEJZiQ2BUlmle4yBNYNYBjTQgkhwFACu0928R+cabrJ9/iCBex+btbXxs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bf+HKq9i; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=V5cYWaC9; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bf+HKq9i"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="V5cYWaC9" Date: Wed, 03 Jun 2026 14:24:58 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780496700; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hWJ6qnN1bhCvSldWOqA4oeru8PXVYQ3SPZHsNxEYT6c=; b=bf+HKq9i3AOHZuJoVRnOsRL56FPSzJlW+8cfAmEtESZxqujPGz0Dl5AaMnwnV/LW/SMNCY phLBlfYoi/236vb+tpvqPUf09og6Jj9gizUEFZXSpEzOtUoe56575d800YAAOjHzCnflf1 tbdMRQASJAZ4DhMZ8Ue3SNr26c1JAzuJgIUm8JQo3p6og/yRJBZ5qFzb+6OllyAKv4frkz CHA9jFsvX/HIC2rUf6Htva9N9cCZz3871LTv3y2KEEnQGU94EDd74agEcFOzD8z/gUjJj7 TJR9DYiyhhUA/uT6GAC1hGC6fWJJnKkLRzfvOeviddyUcyK1N60RKmAQ5wmzqA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780496700; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hWJ6qnN1bhCvSldWOqA4oeru8PXVYQ3SPZHsNxEYT6c=; b=V5cYWaC9QGk59zyNoQoAWok+9TXI32uCmCpFI7h1UOo4+hXoJ9EGcnejrV+v45SP5AFUjL a1NcUM7icmqu+HAg== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] x86: Select ARCH_MEMORY_ORDER_TSO Cc: Thomas Gleixner , "Peter Zijlstra (Intel)" , andrealmeid@igalia.com, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260602090535.564499644@kernel.org> References: <20260602090535.564499644@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178049669865.710.10395805836584770.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: 7b125c44d0b7f617ee81dffd14ce116149d03cb6 Gitweb: https://git.kernel.org/tip/7b125c44d0b7f617ee81dffd14ce11614= 9d03cb6 Author: Thomas Gleixner AuthorDate: Tue, 02 Jun 2026 11:09:47 +02:00 Committer: Peter Zijlstra CommitterDate: Wed, 03 Jun 2026 11:38:50 +02:00 x86: Select ARCH_MEMORY_ORDER_TSO The generic unsafe_atomic_store_release_user() implementation does: if (!IS_ENABLED(CONFIG_ARCH_MEMORY_ORDER_TSO)) smp_mb(); unsafe_put_user(); As x86 implements Total Store Order (TSO) which means stores imply release, select ARCH_MEMORY_ORDER_TSO to avoid the unnecessary smp_mb(). Signed-off-by: Thomas Gleixner Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Andr=C3=A9 Almeida Link: https://patch.msgid.link/20260602090535.564499644@kernel.org --- arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f3f7cb0..1ce62a9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -113,6 +113,7 @@ config X86 select ARCH_HAS_ZONE_DMA_SET if EXPERT select ARCH_HAVE_NMI_SAFE_CMPXCHG select ARCH_HAVE_EXTRA_ELF_NOTES + select ARCH_MEMORY_ORDER_TSO select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI select ARCH_MIGHT_HAVE_PC_PARPORT