From nobody Mon Jun 8 12:13:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8D233CC334; Fri, 29 May 2026 10:45:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780051547; cv=none; b=kLn5tL193uC+adKMOua5FP0mecslTyBZv3pUa32niBGoo6T1HFzCxixS10sEWffoDnN7AbTbzTjzEVO6xah15na5EG2uHR0QEjsCLwJyV0HZ19RtabbXYgYyBCPLd7dw+VYCwxYNk0st1P6jB7nvoCnm10UOG11+aHexqTbiFfQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780051547; c=relaxed/simple; bh=ecnE39Z7qn9Ph6fWQtjB9Du3RC81H4+PgiFhhdc2CO4=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=gn4y4AASd4caLzvbmPo2V6y+ZlR54FZG0iU7UTwb3pT3IqQfoc6Yg4LpISpPq+SiqTKsK1RGRawkwLqmbGffY39C6NPoWHr32SontSXtaEtf/WCOCUSc9g2QziGhzZ9vUCjAhJPNxry6zgP8rciF2xxsYJyPOsDmip90eoCw3sQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iub8v/sA; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ymP6Brdm; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iub8v/sA"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ymP6Brdm" Date: Fri, 29 May 2026 10:45:42 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1780051544; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kaDi35ieaXbA0+dHdx5gnx5/DO7Ao1rC8cskFGrsJK4=; b=iub8v/sAWOpHUdO+D8j662MJ9GqjZusqyIrbfzFwEePls8WqDrCwxkSyTM+TIiH8PpKLK0 u0HtXqru6tNJB3BGC/2qDCvkgNJYJWiVwjmacfBy63Qhm66x1mPWPu6vPsFuT1cnw7jtXH tIDMAGT/+XELnhpNc9e/C2ONr6hAJupRDjsQUFg5h+n3Z1ssXyV0ume9UJoR5qdXW4ASYc poV0mLvzQt82Io9mSYPJP60TFtGfnoY/HBnI0r2MTUjY7gt2QPQxxuqK/Wz10hLYiKrW1J ji8IGc9ynB2KNdfB5wq0ICJP+D2tF65clLQXrrvyRI8Y+4tI3/MZq4Sypw+dXQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1780051544; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kaDi35ieaXbA0+dHdx5gnx5/DO7Ao1rC8cskFGrsJK4=; b=ymP6Brdm2kKEYAYOogct+nyLB3O/l+z0tsMRX9dPQ6/vb0m7T02O9b/I3gFrbqyENCA61M V6A3EwqFUNzMvECg== From: "tip-bot2 for Shrikanth Hegde" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: sched/core] sched/topology: Provide arch_llc_mask for cache aware scheduling Cc: Venkat Rao Bagalkote , Shrikanth Hegde , "Peter Zijlstra (Intel)" , Chen Yu , "Ritesh Harjani (IBM)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260529075712.1181039-1-sshegde@linux.ibm.com> References: <20260529075712.1181039-1-sshegde@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178005154265.1039918.680276051648069396.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the sched/core branch of tip: Commit-ID: 1eae219ea0e80eed83c129e8cae0f007843f1893 Gitweb: https://git.kernel.org/tip/1eae219ea0e80eed83c129e8cae0f0078= 43f1893 Author: Shrikanth Hegde AuthorDate: Fri, 29 May 2026 13:27:12 +05:30 Committer: Peter Zijlstra CommitterDate: Fri, 29 May 2026 12:43:15 +02:00 sched/topology: Provide arch_llc_mask for cache aware scheduling Venkat Reported a boot kernel panic next-20260522. Git bisect pointed to b5ea300a17e3 ("sched/cache: Make LLC id continuous") Stacktrace points to llc_mask being null. NIP [c000000000e58504] _find_first_bit+0x44/0x130 LR [c000000000e58500] _find_first_bit+0x40/0x130 Call Trace: build_sched_domains+0xad8/0xe50 sched_init_smp+0xa8/0x164 kernel_init_freeable+0x250/0x370 ret_from_kernel_user_thread+0x14/0x1c On powerpc, cpu_coregroup_mask is available only when the underlying hardware support coregroup. In shared LPAR, QEMU guest or power9 etc coregroup isn't supported. In such cases llc_mask was being referenced when it was null leading to panic. On powerpc, LLC is at SMT core level. So assumption that coregroup(MC) domain point to LLC is wrong. Provide a way for archs to say where its LLC is if it not at MC domain. Fixes: b5ea300a17e3 ("sched/cache: Make LLC id continuous") Closes: https://lore.kernel.org/all/51154de7-3700-4cb4-82f2-1b3a8fa427f7@li= nux.ibm.com/ Reported-by: Venkat Rao Bagalkote Co-developed-by: Chen, Yu C Signed-off-by: Shrikanth Hegde Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Chen Yu Tested-by: Venkat Rao Bagalkote Tested-by: Ritesh Harjani (IBM) Link: https://patch.msgid.link/20260529075712.1181039-1-sshegde@linux.ibm.c= om --- arch/powerpc/include/asm/topology.h | 7 +++++++ kernel/sched/topology.c | 13 +++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm= /topology.h index 66ed5fe..44ec416 100644 --- a/arch/powerpc/include/asm/topology.h +++ b/arch/powerpc/include/asm/topology.h @@ -135,6 +135,13 @@ struct cpumask *cpu_coregroup_mask(int cpu); const struct cpumask *cpu_die_mask(int cpu); int cpu_die_id(int cpu); =20 +/* + * Points to where the LLC is. On power9 this will point at CACHE + * domain, On others it will point to SMT domain. In all cases + * cpu_l2_cache_mask points to where LLC is + */ +#define arch_llc_mask(cpu) cpu_l2_cache_mask(cpu) + #ifdef CONFIG_PPC64 #include =20 diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index df2ceb5..622e2e0 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -2063,12 +2063,21 @@ const struct cpumask *tl_mc_mask(struct sched_domai= n_topology_level *tl, int cpu return cpu_coregroup_mask(cpu); } =20 -#define llc_mask(cpu) cpu_coregroup_mask(cpu) +/* + * Majority of architectures have LLC at MC domain level with exception + * such as powerpc. Provide a way for arch to specify where its LLC is + * if it falls in exception category + */ +# ifndef arch_llc_mask +#define arch_llc_mask(cpu) cpu_coregroup_mask(cpu) +# endif =20 #else -#define llc_mask(cpu) cpumask_of(cpu) +#define arch_llc_mask(cpu) cpumask_of(cpu) #endif =20 +#define llc_mask(cpu) arch_llc_mask(cpu) + const struct cpumask *tl_pkg_mask(struct sched_domain_topology_level *tl, = int cpu) { return cpu_node_mask(cpu);