From nobody Mon Jun 8 19:54:59 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E6302D6E64; Wed, 27 May 2026 02:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779848668; cv=none; b=ii99kpPObrbBm/dyOvhLur46FG2EjopOsoLNwxF4IsAwKbm8nGQA68PcpyxKE7nVmNg7Zdp7l+mfXfiNo7SMWv20yksBvB+eYvafPIXVz4GS7kcFw2BLQysa8cFKj+zWtYDAe4R7icqVNg8Fk+bbFsjQ1wO3L6lTSxwSU8M/4xA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779848668; c=relaxed/simple; bh=iQHwvIv6MRjre6YBzJZ+DSZ9kQ/CqqMu6EOkvxrgKtU=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=cRUd8A8S22RKCvHIWgf4ObJr9kKhtOw0BY6WRUCVDIYIJxo5O+JBKAAB9Xav7nPM81Swg8eYkeBzuAcnFbXOrnvCquJTRUxbkAwFlmJu+1tPl1LYJzg5o2V+idv8VWRaGjAQE5mXJBc0/GjiBlzoJCXEYHyLzw4JUOUFrxGV9J4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ETmIMwrE; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=z6XhZK/u; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ETmIMwrE"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="z6XhZK/u" Date: Wed, 27 May 2026 02:24:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779848664; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=+aTjqyA+mgbM8YSORAZbM72yN3jWOyxgj+/q5+db08k=; b=ETmIMwrECQ8wA9LIUgNZMOOGsHmTU7i9XOujZoJwFtwKalb0IrYVzSTow79K+yRJM3cNZ0 Wh2mS9Uwf3nOK6HJMJqmZswnELTJDxMNzm9A8+kWAF2enFdN8Zoj/h5vW+W11GGiMjXffb HT0EclIbVDtotHaD7fbk5TfXLdfo3LWtYOXZ2FIESnZH77O/uDnysGZkT0iwqn0hVgq9Kr S4Ec3ef7sJdDvb+y6I7ypsQfUvUKrVkaMsBdv6CFXFulCkXTIIL1sjdm+AFEHuIOq2z++V XHw1PSRETCyRYEXTq8AVeSoAdS9FCnIyaAqD5lyubrCkeuREvCDz762HbFcSiQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779848664; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=+aTjqyA+mgbM8YSORAZbM72yN3jWOyxgj+/q5+db08k=; b=z6XhZK/uHBwpyI93VbfBFmiHbWccguM5p+lvpWNWspAdX9cO8snHWaQ18f/F0Eu9ANjd+e k786hGUnoXqddNAQ== From: "tip-bot2 for Borislav Petkov" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/microcode: Do not access MSR_IA32_PLATFORM_ID when running as a guest Cc: Vishal Verma , "Borislav Petkov (AMD)" , Binbin Wu , Xiaoyao Li , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177984866297.1039918.17173757570262395896.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/urgent branch of tip: Commit-ID: cda64169bade79427f264e43d0f422eaed9dc116 Gitweb: https://git.kernel.org/tip/cda64169bade79427f264e43d0f422eae= d9dc116 Author: Borislav Petkov AuthorDate: Wed, 13 May 2026 22:06:01 +02:00 Committer: Borislav Petkov (AMD) CommitterDate: Tue, 26 May 2026 13:36:23 -07:00 x86/microcode: Do not access MSR_IA32_PLATFORM_ID when running as a guest Patch in Fixes: causes the usual: unchecked MSR access error: RDMSR from 0x17 at ... (intel_get_platform_id) Call Trace: early_init_intel early_cpu_init setup_arch _printk start_kernel x86_64_start_reservations x86_64_start_kernel common_startup_64 because the kernel is booted in a guest. In order to avoid it, this MSR access needs to be prevented when running virtualized. That is usually done by checking X86_FEATURE_HYPERVISOR but for this particular case it is too early yet. The platform ID needs to be read as early as when microcode is loaded on the BSP: load_ucode_bsp ... -> get_microcode_blob ... -> intel_find_matching_signa= ture and by that time, CPUID leafs haven't been parsed yet. The microcode loader already has logic to check early whether the kernel is running virtualized so make that globally available to arch/x86/. The query whether running virtualized is getting more and more prominent in recent times so might as well make it an arch-global var which the rest of the code can use. Fixes: d8630b67ca1ed ("x86/cpu: Add platform ID to CPU info structure") Reported-by: Vishal Verma Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Binbin Wu Reviewed-by: Xiaoyao Li Tested-by: Binbin Wu Link: https://lore.kernel.org/all/20260430020953.1405535-1-binbin.wu@linux.= intel.com --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/microcode/amd.c | 4 ++-- arch/x86/kernel/cpu/microcode/core.c | 22 ++++++++++------------ arch/x86/kernel/cpu/microcode/intel.c | 3 +++ arch/x86/kernel/cpu/microcode/internal.h | 1 - 5 files changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 10b5355..67dd932 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -733,6 +733,7 @@ bool xen_set_default_idle(void); #endif =20 void __noreturn stop_this_cpu(void *dummy); +extern bool x86_hypervisor_present; void microcode_check(struct cpuinfo_x86 *prev_info); void store_cpu_caps(struct cpuinfo_x86 *info); =20 diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/micr= ocode/amd.c index e533881..5c0afae 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -322,7 +322,7 @@ static u32 get_patch_level(void) { u32 rev, dummy __always_unused; =20 - if (IS_ENABLED(CONFIG_MICROCODE_DBG) && hypervisor_present) { + if (IS_ENABLED(CONFIG_MICROCODE_DBG) && x86_hypervisor_present) { int cpu =3D smp_processor_id(); =20 if (!microcode_rev[cpu]) { @@ -714,7 +714,7 @@ static bool __apply_microcode_amd(struct microcode_amd = *mc, u32 *cur_rev, invlpg(p_addr_end); } =20 - if (IS_ENABLED(CONFIG_MICROCODE_DBG) && hypervisor_present) + if (IS_ENABLED(CONFIG_MICROCODE_DBG) && x86_hypervisor_present) microcode_rev[smp_processor_id()] =3D mc->hdr.patch_id; =20 /* verify patch application was successful */ diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 651202e..45ca406 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -57,7 +57,7 @@ bool force_minrev =3D IS_ENABLED(CONFIG_MICROCODE_LATE_FO= RCE_MINREV); u32 base_rev; u32 microcode_rev[NR_CPUS] =3D {}; =20 -bool hypervisor_present; +bool __ro_after_init x86_hypervisor_present; =20 /* * Synchronization. @@ -118,14 +118,9 @@ bool __init microcode_loader_disabled(void) /* * Disable when: * - * 1) The CPU does not support CPUID. - */ - if (!cpuid_feature()) { - dis_ucode_ldr =3D true; - return dis_ucode_ldr; - } - - /* + * 1) The CPU does not support CPUID, detected below in + * load_ucode_bsp(). + * * 2) Bit 31 in CPUID[1]:ECX is clear * The bit is reserved for hypervisor use. This is still not * completely accurate as XEN PV guests don't see that CPUID bit @@ -135,9 +130,7 @@ bool __init microcode_loader_disabled(void) * 3) Certain AMD patch levels are not allowed to be * overwritten. */ - hypervisor_present =3D native_cpuid_ecx(1) & BIT(31); - - if ((hypervisor_present && !IS_ENABLED(CONFIG_MICROCODE_DBG)) || + if ((x86_hypervisor_present && !IS_ENABLED(CONFIG_MICROCODE_DBG)) || amd_check_current_patch_level()) dis_ucode_ldr =3D true; =20 @@ -179,6 +172,11 @@ void __init load_ucode_bsp(void) =20 early_parse_cmdline(); =20 + if (!cpuid_feature()) + dis_ucode_ldr =3D true; + else + x86_hypervisor_present =3D native_cpuid_ecx(1) & BIT(31); + if (microcode_loader_disabled()) return; =20 diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 37ac4af..a4c0a0c 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -138,6 +138,9 @@ u32 intel_get_platform_id(void) { unsigned int val[2]; =20 + if (x86_hypervisor_present) + return 0; + /* * This can be called early. Use CPUID directly instead of * relying on cpuinfo_x86 which may not be fully initialized. diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 3b93c06..a10b547 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -48,7 +48,6 @@ extern struct early_load_data early_data; extern struct ucode_cpu_info ucode_cpu_info[]; extern u32 microcode_rev[NR_CPUS]; extern u32 base_rev; -extern bool hypervisor_present; =20 struct cpio_data find_microcode_in_initrd(const char *path); =20