From nobody Mon Jun 8 20:42:47 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37D9D402442; Tue, 26 May 2026 14:22:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779805359; cv=none; b=aKzyiwsNNr4UPQqjZeCA4+4qr1WdAYLWfyZXXN32+1K44dqNrWB6lEKUG5PweJJQQCAbU/LSrkFOrF3ol3Zyp2BsHh71Zh6/orZHmgEd+2QvxDdPfQBMSEOj7bfp1xyqzva9oIaCzMrkV/QyhuyV1P/Dt9riEVXp0B31uSQB7CM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779805359; c=relaxed/simple; bh=j1+gN4RgZGaieUt94gLPcWSGfVS1klbjSoyw0SzUCzk=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Yin6xsVuKABe5SLfTFvdlDUxWX4FJ3DZA00BTLsfHmoJxPBS8elXzI5hDDf7hHNB/GDeu2Fh8o8b2yvj4l1BwfFVJG4+4jKYBdncsjVpUSMRzxyjNM+KFj3LSUuwborXYUxomfwvJyQRraJFNsZlo8dyogRPkQYhSTxkkJzyGYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0nm5pX0S; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=L22zXEUW; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0nm5pX0S"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="L22zXEUW" Date: Tue, 26 May 2026 14:22:33 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779805354; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m5HflzbNmJEPgAPjuzulO6y+NPdQSSCq7mxmOf3i3jI=; b=0nm5pX0Sz5jCEO30658qyNXByFMKvczqe0TN3X6xJazsa0EScUY0sbFrqrgUE/jMToTO+3 b6SVnYzLPyYK8z47v+SH0lcZqWsJaEj/2fhv/LFdK0EIumW0coGZS1nt0V+VBsocnr/CLJ lM9QGN3ju8sg0+GqJ+eXIVRcgFWksi0MNlv+kHa8O8m3YSxqkFs3e2gOzMd5GmN/JCHFJH 7XKy2VTNdJUYQvqyghD09NoXq+OQOrlPvSt5UM5BVedDpyLZ8VnFuR2z9TOU0ZXa2zEyLY SHLaCoC59xcgooBM1Pm6hWRBdut36nkjAyXQ2/5m1hgqY4MvyEeYLcsovolsXg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779805354; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m5HflzbNmJEPgAPjuzulO6y+NPdQSSCq7mxmOf3i3jI=; b=L22zXEUWifuUhg+McdDnr3kTKKDxYqRFcAINe7uRtIUzI91eSPMjpohLoiy7xxGDQzYWiE cFmL+OqbPibNmXDA== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] x86/irq: Suppress unlikely interrupt stats by default Cc: Thomas Gleixner , Michael Kelley , Radu Rendec , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20260517194931.276486277@kernel.org> References: <20260517194931.276486277@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177980535315.1039918.4136900285564178037.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/core branch of tip: Commit-ID: 8713f2e596a134ed5c41e96bb9714251a5e6d56a Gitweb: https://git.kernel.org/tip/8713f2e596a134ed5c41e96bb9714251a= 5e6d56a Author: Thomas Gleixner AuthorDate: Sun, 17 May 2026 22:01:54 +02:00 Committer: Thomas Gleixner CommitterDate: Tue, 26 May 2026 16:21:12 +02:00 x86/irq: Suppress unlikely interrupt stats by default Unlikely interrupt counters like the spurious vector and the synthetic APIC ICR read retry show up in /proc/interrupts with all counts 0 most of the time. As these are events which should never happen, suppress them by default and enable them for output when they actually happen. This requires a seperate bitmap as the description array is marked __ro_after_init. With that bitmap in place it becomes RO data. Signed-off-by: Thomas Gleixner Tested-by: Michael Kelley Reviewed-by: Radu Rendec Link: https://patch.msgid.link/20260517194931.276486277@kernel.org --- arch/x86/include/asm/hardirq.h | 1 +- arch/x86/kernel/apic/apic.c | 2 +- arch/x86/kernel/apic/ipi.c | 2 +- arch/x86/kernel/irq.c | 38 ++++++++++++++++++++++++--------- 4 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h index 423fa4d..6723b51 100644 --- a/arch/x86/include/asm/hardirq.h +++ b/arch/x86/include/asm/hardirq.h @@ -68,6 +68,7 @@ DECLARE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_des= c); #define __ARCH_IRQ_STAT =20 #define inc_irq_stat(index) this_cpu_inc(irq_stat.counts[IRQ_COUNT_##index= ]) +void irq_stat_inc_and_enable(enum irq_stat_counts which); =20 #ifdef CONFIG_X86_LOCAL_APIC #define inc_perf_irq_stat() inc_irq_stat(APIC_PERF) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 6599e80..e27c263 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2114,7 +2114,7 @@ static noinline void handle_spurious_interrupt(u8 vec= tor) =20 trace_spurious_apic_entry(vector); =20 - inc_irq_stat(SPURIOUS); + irq_stat_inc_and_enable(IRQ_COUNT_SPURIOUS); =20 /* * If this is a spurious interrupt then do not acknowledge diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 3635c4d..c627bee 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -120,7 +120,7 @@ u32 apic_mem_wait_icr_idle_timeout(void) for (cnt =3D 0; cnt < 1000; cnt++) { if (!(apic_read(APIC_ICR) & APIC_ICR_BUSY)) return 0; - inc_irq_stat(ICR_READ_RETRY); + irq_stat_inc_and_enable(IRQ_COUNT_ICR_READ_RETRY); udelay(100); } return APIC_ICR_BUSY; diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index decd08d..2d8ca41 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -68,19 +68,24 @@ struct irq_stat_info { const char *text; }; =20 +#define DEFAULT_SUPPRESSED_VECTOR UINT_MAX + #define ISS(idx, sym, txt) [IRQ_COUNT_##idx] =3D { .symbol =3D sym, .text = =3D txt } =20 #define ITS(idx, sym, txt) [IRQ_COUNT_##idx] =3D \ { .skip_vector =3D idx## _VECTOR, .symbol =3D sym, .text =3D txt } =20 -static struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] __ro_after_init = =3D { +#define IDS(idx, sym, txt) [IRQ_COUNT_##idx] =3D \ + { .skip_vector =3D DEFAULT_SUPPRESSED_VECTOR, .symbol =3D sym, .text =3D = txt } + +static const struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] =3D { ISS(NMI, "NMI", " Non-maskable interrupts\n"), #ifdef CONFIG_X86_LOCAL_APIC ISS(APIC_TIMER, "LOC", " Local timer interrupts\n"), - ISS(SPURIOUS, "SPU", " Spurious interrupts\n"), + IDS(SPURIOUS, "SPU", " Spurious interrupts\n"), ISS(APIC_PERF, "PMI", " Performance monitoring interrupts\n"), ISS(IRQ_WORK, "IWI", " IRQ work interrupts\n"), - ISS(ICR_READ_RETRY, "RTR", " APIC ICR read retries\n"), + IDS(ICR_READ_RETRY, "RTR", " APIC ICR read retries\n"), ISS(X86_PLATFORM_IPI, "PLT", " Platform interrupts\n"), #endif #ifdef CONFIG_SMP @@ -121,34 +126,47 @@ static struct irq_stat_info irq_stat_info[IRQ_COUNT_M= AX] __ro_after_init =3D { #endif }; =20 +static DECLARE_BITMAP(irq_stat_count_show, IRQ_COUNT_MAX) __read_mostly; + static int __init irq_init_stats(void) { - struct irq_stat_info *info =3D irq_stat_info; + const struct irq_stat_info *info =3D irq_stat_info; =20 for (unsigned int i =3D 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) { - if (info->skip_vector && test_bit(info->skip_vector, system_vectors)) - info->skip_vector =3D 0; + if (!info->skip_vector || (info->skip_vector !=3D DEFAULT_SUPPRESSED_VEC= TOR && + test_bit(info->skip_vector, system_vectors))) + set_bit(i, irq_stat_count_show); } =20 #ifdef CONFIG_X86_LOCAL_APIC if (!x86_platform_ipi_callback) - irq_stat_info[IRQ_COUNT_X86_PLATFORM_IPI].skip_vector =3D 1; + clear_bit(IRQ_COUNT_X86_PLATFORM_IPI, irq_stat_count_show); #endif =20 #ifdef CONFIG_X86_POSTED_MSI if (!posted_msi_enabled()) - irq_stat_info[IRQ_COUNT_POSTED_MSI_NOTIFICATION].skip_vector =3D 1; + clear_bit(IRQ_COUNT_POSTED_MSI_NOTIFICATION, irq_stat_count_show); #endif =20 #ifdef CONFIG_X86_MCE_AMD if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) - irq_stat_info[IRQ_COUNT_DEFERRED_ERROR].skip_vector =3D 1; + clear_bit(IRQ_COUNT_DEFERRED_ERROR, irq_stat_count_show); #endif return 0; } late_initcall(irq_init_stats); =20 +/* + * Used for default disabled counters to increment the stats and to enable= the + * entry for /proc/interrupts output. + */ +void irq_stat_inc_and_enable(enum irq_stat_counts which) +{ + this_cpu_inc(irq_stat.counts[which]); + set_bit(which, irq_stat_count_show); +} + #ifdef CONFIG_PROC_FS /* * /proc/interrupts printing for arch specific interrupts @@ -158,7 +176,7 @@ int arch_show_interrupts(struct seq_file *p, int prec) const struct irq_stat_info *info =3D irq_stat_info; =20 for (unsigned int i =3D 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) { - if (info->skip_vector) + if (!test_bit(i, irq_stat_count_show)) continue; =20 seq_printf(p, "%*s:", prec, info->symbol);