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Tue, 26 May 2026 03:47:38 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Tue, 26 May 2026 03:47:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Tue, 26 May 2026 03:47:37 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id 2A5243F7052; Tue, 26 May 2026 03:47:33 -0700 (PDT) From: Subbaraya Sundeep To: , , , , , , , CC: , , "Subbaraya Sundeep" Subject: [net-next PATCH v6 1/5] octeontx2-af: Simplify NPA context writing and reading Date: Tue, 26 May 2026 16:17:23 +0530 Message-ID: <1779792447-5593-2-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1779792447-5593-1-git-send-email-sbhatta@marvell.com> References: <1779792447-5593-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=epTvCIpX c=1 sm=1 tr=0 ts=6a157a4a cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=M5GUcnROAAAA:8 a=Hh8S9ZQ4bCWoy7TokGkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: zplzl9E80eg9ytQhxjXTTtfDCIrDue6C X-Proofpoint-GUID: zplzl9E80eg9ytQhxjXTTtfDCIrDue6C X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA5MyBTYWx0ZWRfX7I21BPtOu3hl BepsBA7Jg/Cj53y8mn0ZNMQSP3NWJ+fA51z2dDp0JHpYILvHcwUAMQOXUx4nJFPunTZfNrHBXjR HLUeMj7tWNJhWL4VuUj/GIbYETaSR/OA4z6J6VLJ0xCyz53TsOTMBBmCCCjgzDNBhQEhTVLjK9F tMqEWksm/3Fc3p46WWPyLp4IqCurtqLJkjKm0SfPNku1GGXRhTgBrX6bxy6zUCiiwsB3/5sSM40 Khkgsc5QfXJP0gK6+n4Wp9o0jKDG7GVnLhsxCVAp0rWfXdTXOcgTG+fk/XsZpDgKhDTPh5WrgT7 qZJQaii0UJrTueFowrajQiW8z5+fWOy/toqXY7yT+QeAPyucRziwpZkOs4jgDAJdZTY46DzDstg I/il4HhqrLz05hLTS8gGPxnR6zygzNfx9fsbhF7im2tnqXy/mdVmhSBjl49ftMRsSZza7YBHrJt LPc192AadeC3XkZU4AQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-26_02,2026-05-26_01,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify NPA context reading and writing by using hardware maximum context size instead of using individual sizes of each context type. Signed-off-by: Subbaraya Sundeep --- .../ethernet/marvell/octeontx2/af/rvu_npa.c | 20 ++++++++----------- .../marvell/octeontx2/af/rvu_struct.h | 6 ++++++ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npa.c index e2a33e46b48a..df783c4e5d75 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c @@ -116,13 +116,11 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_a= q_enq_req *req, case NPA_AQ_INSTOP_WRITE: /* Copy context and write mask */ if (req->ctype =3D=3D NPA_AQ_CTYPE_AURA) { - memcpy(mask, &req->aura_mask, - sizeof(struct npa_aura_s)); - memcpy(ctx, &req->aura, sizeof(struct npa_aura_s)); + memcpy(mask, &req->aura_mask, NIX_MAX_CTX_SIZE); + memcpy(ctx, &req->aura, NIX_MAX_CTX_SIZE); } else { - memcpy(mask, &req->pool_mask, - sizeof(struct npa_pool_s)); - memcpy(ctx, &req->pool, sizeof(struct npa_pool_s)); + memcpy(mask, &req->pool_mask, NIX_MAX_CTX_SIZE); + memcpy(ctx, &req->pool, NIX_MAX_CTX_SIZE); } break; case NPA_AQ_INSTOP_INIT: @@ -134,9 +132,9 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, /* Set pool's context address */ req->aura.pool_addr =3D pfvf->pool_ctx->iova + (req->aura.pool_addr * pfvf->pool_ctx->entry_sz); - memcpy(ctx, &req->aura, sizeof(struct npa_aura_s)); + memcpy(ctx, &req->aura, NIX_MAX_CTX_SIZE); } else { /* POOL's context */ - memcpy(ctx, &req->pool, sizeof(struct npa_pool_s)); + memcpy(ctx, &req->pool, NIX_MAX_CTX_SIZE); } break; case NPA_AQ_INSTOP_NOP: @@ -196,11 +194,9 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq= _enq_req *req, /* Copy read context into mailbox */ if (req->op =3D=3D NPA_AQ_INSTOP_READ) { if (req->ctype =3D=3D NPA_AQ_CTYPE_AURA) - memcpy(&rsp->aura, ctx, - sizeof(struct npa_aura_s)); + memcpy(&rsp->aura, ctx, NIX_MAX_CTX_SIZE); else - memcpy(&rsp->pool, ctx, - sizeof(struct npa_pool_s)); + memcpy(&rsp->pool, ctx, NIX_MAX_CTX_SIZE); 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Tue, 26 May 2026 03:47:42 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Tue, 26 May 2026 03:47:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Tue, 26 May 2026 03:47:41 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id 11B223F7051; Tue, 26 May 2026 03:47:37 -0700 (PDT) From: Subbaraya Sundeep To: , , , , , , , CC: , , Linu Cherian , Subbaraya Sundeep Subject: [net-next PATCH v6 2/5] octeontx2-af: npa: cn20k: Add NPA Halo support Date: Tue, 26 May 2026 16:17:24 +0530 Message-ID: <1779792447-5593-3-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1779792447-5593-1-git-send-email-sbhatta@marvell.com> References: <1779792447-5593-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=BK6DalQG c=1 sm=1 tr=0 ts=6a157a4e cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=K_mExLjy7pjPs-0ftoIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: FWSFykoR9ji2HUOTPwEvZ5XE_Xc_n1im X-Proofpoint-ORIG-GUID: FWSFykoR9ji2HUOTPwEvZ5XE_Xc_n1im X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA5MyBTYWx0ZWRfX+GK8Lj9LO4Jc 4nWik2TIyfnwbRp/m6IuGt+Xs1GqXFN23Ghrr2+i9cWzPw+Xyd+CyCCUvxz2FXogeHy+TrqTTbn 5YCplzLppaDgv/s/KqS+QSlc8YE0z/my5RyROkoskTl245FFCO69Xemo+5TL5rqpSWlTIF7UiFJ f1o4G1q0ttJA7kJUggFQ0vLrZ3f+mq3lhZjXxbCSvLodSFTQgTgj7HDBTHMmgWo7YYbdjea5Dii FL5WSchYqJhrEIUuh71/2T03YGeg3eBo9jisn2aKaaOv8gGPsmbilxr/JZtKEfPcrCKytKPuv0T 7ixH98J6sJpotB1HOyRWqGysc/d71v46JGknJNmalXvB2gREvBzjxIkzM3hbdQbfuwo/N+OG6FK ucPN+3lSH80SDkk7PfGnsW5r0XORNXMovD1v/god2HX3dLm/ry4GuAIqZ0BzAvSbB9gtNb45Jax gaR10SqwSUTWL/lJpXw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-26_02,2026-05-26_01,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Linu Cherian CN20K silicon implements unified aura and pool context type called Halo for better resource usage. Add support to handle Halo context type operations. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../marvell/octeontx2/af/cn20k/struct.h | 81 +++++++++++++++++++ .../net/ethernet/marvell/octeontx2/af/mbox.h | 6 ++ .../net/ethernet/marvell/octeontx2/af/rvu.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_npa.c | 59 ++++++++++++-- .../marvell/octeontx2/af/rvu_struct.h | 1 + 5 files changed, 141 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h b/dri= vers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h index 763f6cabd7c2..2364bafd329d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h @@ -377,4 +377,85 @@ struct npa_cn20k_pool_s { =20 static_assert(sizeof(struct npa_cn20k_pool_s) =3D=3D NIX_MAX_CTX_SIZE); =20 +struct npa_cn20k_halo_s { + u64 stack_base : 64; + u64 ena : 1; + u64 nat_align : 1; + u64 reserved_66_67 : 2; + u64 stack_caching : 1; + u64 reserved_69_71 : 3; + u64 aura_drop_ena : 1; + u64 reserved_73_79 : 7; + u64 aura_drop : 8; + u64 buf_offset : 12; + u64 reserved_100_103 : 4; + u64 buf_size : 12; + u64 reserved_116_119 : 4; + u64 ref_cnt_prof : 3; + u64 reserved_123_127 : 5; + u64 stack_max_pages : 32; + u64 stack_pages : 32; + u64 bp_0 : 7; + u64 bp_1 : 7; + u64 bp_2 : 7; + u64 bp_3 : 7; + u64 bp_4 : 7; + u64 bp_5 : 7; + u64 bp_6 : 7; + u64 bp_7 : 7; + u64 bp_ena_0 : 1; + u64 bp_ena_1 : 1; + u64 bp_ena_2 : 1; + u64 bp_ena_3 : 1; + u64 bp_ena_4 : 1; + u64 bp_ena_5 : 1; + u64 bp_ena_6 : 1; + u64 bp_ena_7 : 1; + u64 stack_offset : 4; + u64 reserved_260_263 : 4; + u64 shift : 6; + u64 reserved_270_271 : 2; + u64 avg_level : 8; + u64 avg_con : 9; + u64 fc_ena : 1; + u64 fc_stype : 2; + u64 fc_hyst_bits : 4; + u64 fc_up_crossing : 1; + u64 reserved_297_299 : 3; + u64 update_time : 16; + u64 reserved_316_319 : 4; + u64 fc_addr : 64; + u64 ptr_start : 64; + u64 ptr_end : 64; + u64 bpid_0 : 12; + u64 reserved_524_535 : 12; + u64 err_int : 8; + u64 err_int_ena : 8; + u64 thresh_int : 1; + u64 thresh_int_ena : 1; + u64 thresh_up : 1; + u64 reserved_555 : 1; + u64 thresh_qint_idx : 7; + u64 reserved_563 : 1; + u64 err_qint_idx : 7; + u64 reserved_571_575 : 5; + u64 thresh : 36; + u64 reserved_612_615 : 4; + u64 fc_msh_dst : 11; + u64 reserved_627_630 : 4; + u64 op_dpc_ena : 1; + u64 op_dpc_set : 5; + u64 reserved_637_637 : 1; + u64 stream_ctx : 1; + u64 unified_ctx : 1; + u64 reserved_640_703 : 64; + u64 reserved_704_767 : 64; + u64 reserved_768_831 : 64; + u64 reserved_832_895 : 64; + u64 reserved_896_959 : 64; + u64 reserved_960_1023 : 64; +}; + +static_assert(sizeof(struct npa_cn20k_halo_s) =3D=3D NIX_MAX_CTX_SIZE); + #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index dc42c81c0942..4a97bd93d882 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -884,6 +884,8 @@ struct npa_cn20k_aq_enq_req { struct npa_cn20k_aura_s aura; /* Valid when op =3D=3D WRITE/INIT and ctype =3D=3D POOL */ struct npa_cn20k_pool_s pool; + /* Valid when op =3D=3D WRITE/INIT and ctype =3D=3D HALO */ + struct npa_cn20k_halo_s halo; }; /* Mask data when op =3D=3D WRITE (1=3Dwrite, 0=3Ddon't write) */ union { @@ -891,6 +893,8 @@ struct npa_cn20k_aq_enq_req { struct npa_cn20k_aura_s aura_mask; /* Valid when op =3D=3D WRITE and ctype =3D=3D POOL */ struct npa_cn20k_pool_s pool_mask; + /* Valid when op =3D=3D WRITE/INIT and ctype =3D=3D HALO */ + struct npa_cn20k_halo_s halo_mask; }; }; =20 @@ -901,6 +905,8 @@ struct npa_cn20k_aq_enq_rsp { struct npa_cn20k_aura_s aura; /* Valid when op =3D=3D READ and ctype =3D=3D POOL */ struct npa_cn20k_pool_s pool; + /* Valid when op =3D=3D READ and ctype =3D=3D HALO */ + struct npa_cn20k_halo_s halo; }; }; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index a466181cf908..0c4dae6d0967 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -261,6 +261,7 @@ struct rvu_pfvf { struct qmem *pool_ctx; struct qmem *npa_qints_ctx; unsigned long *aura_bmap; + unsigned long *halo_bmap; unsigned long *pool_bmap; =20 /* NIX contexts */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npa.c index df783c4e5d75..d15e6969ee56 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c @@ -12,6 +12,11 @@ #include "rvu_reg.h" #include "rvu.h" =20 +static bool npa_ctype_invalid(struct rvu *rvu, int ctype) +{ + return !is_cn20k(rvu->pdev) && ctype =3D=3D NPA_AQ_CTYPE_HALO; +} + static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, struct npa_aq_inst_s *inst) { @@ -72,7 +77,8 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_en= q_req *req, bool ena; =20 pfvf =3D rvu_get_pfvf(rvu, pcifunc); - if (!pfvf->aura_ctx || req->aura_id >=3D pfvf->aura_ctx->qsize) + if (!pfvf->aura_ctx || req->aura_id >=3D pfvf->aura_ctx->qsize || + npa_ctype_invalid(rvu, req->ctype)) return NPA_AF_ERR_AQ_ENQUEUE; =20 blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); @@ -118,7 +124,7 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, if (req->ctype =3D=3D NPA_AQ_CTYPE_AURA) { memcpy(mask, &req->aura_mask, NIX_MAX_CTX_SIZE); memcpy(ctx, &req->aura, NIX_MAX_CTX_SIZE); - } else { + } else { /* Applies to pool and halo since size is same */ memcpy(mask, &req->pool_mask, NIX_MAX_CTX_SIZE); memcpy(ctx, &req->pool, NIX_MAX_CTX_SIZE); } @@ -133,7 +139,7 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, req->aura.pool_addr =3D pfvf->pool_ctx->iova + (req->aura.pool_addr * pfvf->pool_ctx->entry_sz); memcpy(ctx, &req->aura, NIX_MAX_CTX_SIZE); - } else { /* POOL's context */ + } else { /* Applies to pool and halo since size is same */ memcpy(ctx, &req->pool, NIX_MAX_CTX_SIZE); } break; @@ -174,6 +180,20 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq= _enq_req *req, } } =20 + if (req->ctype =3D=3D NPA_AQ_CTYPE_HALO) { + if (req->op =3D=3D NPA_AQ_INSTOP_INIT && req->aura.ena) + __set_bit(req->aura_id, pfvf->halo_bmap); + if (req->op =3D=3D NPA_AQ_INSTOP_WRITE) { + ena =3D (req->aura.ena & req->aura_mask.ena) | + (test_bit(req->aura_id, pfvf->halo_bmap) & + ~req->aura_mask.ena); + if (ena) + __set_bit(req->aura_id, pfvf->halo_bmap); + else + __clear_bit(req->aura_id, pfvf->halo_bmap); + } + } + /* Set pool bitmap if pool hw context is enabled */ if (req->ctype =3D=3D NPA_AQ_CTYPE_POOL) { if (req->op =3D=3D NPA_AQ_INSTOP_INIT && req->pool.ena) @@ -195,7 +215,7 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_= enq_req *req, if (req->op =3D=3D NPA_AQ_INSTOP_READ) { if (req->ctype =3D=3D NPA_AQ_CTYPE_AURA) memcpy(&rsp->aura, ctx, NIX_MAX_CTX_SIZE); - else + else /* Applies to pool and halo since size is same */ memcpy(&rsp->pool, ctx, NIX_MAX_CTX_SIZE); } } @@ -206,12 +226,14 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_a= q_enq_req *req, static int npa_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req = *req) { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, req->hdr.pcifunc); + const char *context =3D "Unknown"; struct npa_aq_enq_req aq_req; unsigned long *bmap; int id, cnt =3D 0; int err =3D 0, rc; =20 - if (!pfvf->pool_ctx || !pfvf->aura_ctx) + if (!pfvf->pool_ctx || !pfvf->aura_ctx || + npa_ctype_invalid(rvu, req->ctype)) return NPA_AF_ERR_AQ_ENQUEUE; =20 memset(&aq_req, 0, sizeof(struct npa_aq_enq_req)); @@ -222,6 +244,7 @@ static int npa_lf_hwctx_disable(struct rvu *rvu, struct= hwctx_disable_req *req) aq_req.pool_mask.ena =3D 1; cnt =3D pfvf->pool_ctx->qsize; bmap =3D pfvf->pool_bmap; + context =3D "Pool"; } else if (req->ctype =3D=3D NPA_AQ_CTYPE_AURA) { aq_req.aura.ena =3D 0; aq_req.aura_mask.ena =3D 1; @@ -229,6 +252,13 @@ static int npa_lf_hwctx_disable(struct rvu *rvu, struc= t hwctx_disable_req *req) aq_req.aura_mask.bp_ena =3D 1; cnt =3D pfvf->aura_ctx->qsize; bmap =3D pfvf->aura_bmap; + context =3D "Aura"; + } else if (req->ctype =3D=3D NPA_AQ_CTYPE_HALO) { + aq_req.aura.ena =3D 0; + aq_req.aura_mask.ena =3D 1; + cnt =3D pfvf->aura_ctx->qsize; + bmap =3D pfvf->halo_bmap; + context =3D "Halo"; } =20 aq_req.ctype =3D req->ctype; @@ -242,8 +272,7 @@ static int npa_lf_hwctx_disable(struct rvu *rvu, struct= hwctx_disable_req *req) if (rc) { err =3D rc; dev_err(rvu->dev, "Failed to disable %s:%d context\n", - (req->ctype =3D=3D NPA_AQ_CTYPE_AURA) ? - "Aura" : "Pool", id); + context, id); } } =20 @@ -307,6 +336,9 @@ static void npa_ctx_free(struct rvu *rvu, struct rvu_pf= vf *pfvf) kfree(pfvf->aura_bmap); pfvf->aura_bmap =3D NULL; =20 + kfree(pfvf->halo_bmap); + pfvf->halo_bmap =3D NULL; + qmem_free(rvu->dev, pfvf->aura_ctx); pfvf->aura_ctx =3D NULL; =20 @@ -370,6 +402,13 @@ int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, if (!pfvf->aura_bmap) goto free_mem; =20 + if (is_cn20k(rvu->pdev)) { + pfvf->halo_bmap =3D kcalloc(NPA_AURA_COUNT(req->aura_sz), + sizeof(long), GFP_KERNEL); + if (!pfvf->halo_bmap) + goto free_mem; + } + /* Alloc memory for pool HW contexts */ hwctx_size =3D 1UL << ((ctx_cfg >> 4) & 0xF); err =3D qmem_alloc(rvu->dev, &pfvf->pool_ctx, req->nr_pools, hwctx_size); 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Tue, 26 May 2026 03:47:46 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Tue, 26 May 2026 03:47:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Tue, 26 May 2026 03:47:45 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id 39C163F7052; Tue, 26 May 2026 03:47:41 -0700 (PDT) From: Subbaraya Sundeep To: , , , , , , , CC: , , Linu Cherian , Subbaraya Sundeep Subject: [net-next PATCH v6 3/5] octeontx2-af: npa: cn20k: Add DPC support Date: Tue, 26 May 2026 16:17:25 +0530 Message-ID: <1779792447-5593-4-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1779792447-5593-1-git-send-email-sbhatta@marvell.com> References: <1779792447-5593-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=epTvCIpX c=1 sm=1 tr=0 ts=6a157a53 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=M5GUcnROAAAA:8 a=MAZRZ2gKoPIzyDCOxB0A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: mIYPf1Vr6sjB4SbcCrEmEixXZvr4hie9 X-Proofpoint-GUID: mIYPf1Vr6sjB4SbcCrEmEixXZvr4hie9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI2MDA5MyBTYWx0ZWRfX6nMaD0yIz79L FQvoUHG6IGsFETmTfEWO53VRnMZtHwjePXpiSw0WXk414smtgdpCVPaJ+4NL8JmFf5skLyaowe0 UAw9fezWcwVp/0JRh4Ppck2nts4WlbMOO2AHSDWMpitax+Ac5kcaAdEMT0pyGOogzpyUBRA3Lfi JD+go1kySQCdS5YXzmWFx2ZEzjVhLn5WYm23tFuW1uBqJgukZvPLet0SHskRlsq2qi7c+aCgot/ 7qzYCYTabey85X40JokCEjGXG511xTQuZJqvCkR/vlTCHrG8JhvyJI/vw5Og+dbOPPxCjdlVtOh ENHhf2xCU/T+Kxf5dix0Q3U6RX6OdAQN1x8EU8k5hSq1bFHzf4qhkDJCghrwe/NEXwac9VUo9lf SL1EeCqq05JHhHX1PQ71P4r24akXfI8sQ6mTM10fqUxEGlsuv6wYDbQ/ljmfeUAkFgpXJ5AHh/A Ef1glktDl0FoCgDtlQA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-26_02,2026-05-26_01,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Linu Cherian CN20k introduces 32 diagnostic and performance counters that are shared across all NPA LFs. Counters being shared, each PF driver need to request for a counter with the required configuration to the AF, so that a counter can be allocated and mapped to the respective LF with the requested configuration. Add new mbox messages, npa_dpc_alloc/free to handle this. Also ensure all the LF to DPC counter mappings are cleared at the time of LF free/teardown. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../ethernet/marvell/octeontx2/af/cn20k/api.h | 3 + .../ethernet/marvell/octeontx2/af/cn20k/npa.c | 139 ++++++++++++++++++ .../ethernet/marvell/octeontx2/af/cn20k/reg.h | 7 + .../net/ethernet/marvell/octeontx2/af/mbox.h | 19 +++ .../net/ethernet/marvell/octeontx2/af/rvu.h | 3 + .../ethernet/marvell/octeontx2/af/rvu_npa.c | 17 ++- 6 files changed, 187 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/api.h index 4285b5d6a6a2..53050f63eb81 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/api.h @@ -29,4 +29,7 @@ int cn20k_mbox_setup(struct otx2_mbox *mbox, struct pci_d= ev *pdev, void *reg_base, int direction, int ndevs); void cn20k_rvu_enable_afvf_intr(struct rvu *rvu, int vfs); void cn20k_rvu_disable_afvf_intr(struct rvu *rvu, int vfs); + +void npa_cn20k_dpc_free_all(struct rvu *rvu, u16 pcifunc); + #endif /* CN20K_API_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/npa.c index fe8f926c8b75..7c9cd28de3ee 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npa.c @@ -8,6 +8,8 @@ #include #include =20 +#include "cn20k/api.h" +#include "cn20k/reg.h" #include "struct.h" #include "../rvu.h" =20 @@ -19,3 +21,140 @@ int rvu_mbox_handler_npa_cn20k_aq_enq(struct rvu *rvu, (struct npa_aq_enq_rsp *)rsp); } EXPORT_SYMBOL(rvu_mbox_handler_npa_cn20k_aq_enq); + +static int npa_cn20k_dpc_alloc(struct rvu *rvu, + struct npa_cn20k_dpc_alloc_req *req, + struct npa_cn20k_dpc_alloc_rsp *rsp) +{ + struct rvu_hwinfo *hw =3D rvu->hw; + u16 pcifunc =3D req->hdr.pcifunc; + int cntr, lf, blkaddr, ridx; + struct rvu_block *block; + struct rvu_pfvf *pfvf; + u64 val, lfmask; + + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); + if (!pfvf->npalf || blkaddr < 0) + return NPA_AF_ERR_AF_LF_INVALID; + + mutex_lock(&rvu->rsrc_lock); + + block =3D &hw->block[blkaddr]; + lf =3D rvu_get_lf(rvu, block, pcifunc, 0); + if (lf < 0) { + mutex_unlock(&rvu->rsrc_lock); + return NPA_AF_ERR_AF_LF_INVALID; + } + + /* allocate a new counter */ + cntr =3D rvu_alloc_rsrc(&rvu->npa_dpc); + if (cntr < 0) { + mutex_unlock(&rvu->rsrc_lock); + return cntr; + } + + rsp->cntr_id =3D cntr; + + /* Consumers can configure to count ALLOC/FREE requests only */ + rvu_write64(rvu, blkaddr, NPA_AF_DPCX_CFG(cntr), req->dpc_conf); + + /* 0 to 63 lfs -> idx 0, 64 - 127 lfs -> idx 1 */ + ridx =3D lf >> 6; + lfmask =3D BIT_ULL(ridx ? lf - NPA_DPC_LFS_PER_REG : lf); + + ridx =3D 2 * cntr + ridx; + /* Give permission for LF access */ + val =3D rvu_read64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx)); + val |=3D lfmask; + rvu_write64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx), val); + + mutex_unlock(&rvu->rsrc_lock); + + return 0; +} + +int rvu_mbox_handler_npa_cn20k_dpc_alloc(struct rvu *rvu, + struct npa_cn20k_dpc_alloc_req *req, + struct npa_cn20k_dpc_alloc_rsp *rsp) +{ + if (!is_cn20k(rvu->pdev)) + return -EOPNOTSUPP; + + return npa_cn20k_dpc_alloc(rvu, req, rsp); +} + +static int npa_cn20k_dpc_free(struct rvu *rvu, + struct npa_cn20k_dpc_free_req *req) +{ + struct rvu_hwinfo *hw =3D rvu->hw; + u16 pcifunc =3D req->hdr.pcifunc; + int cntr, lf, blkaddr, ridx; + struct rvu_block *block; + struct rvu_pfvf *pfvf; + u64 val, lfmask; + + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); + if (!pfvf->npalf || blkaddr < 0) + return NPA_AF_ERR_AF_LF_INVALID; + + block =3D &hw->block[blkaddr]; + lf =3D rvu_get_lf(rvu, block, pcifunc, 0); + if (lf < 0) + return NPA_AF_ERR_AF_LF_INVALID; + + if (req->cntr_id >=3D NPA_DPC_MAX) + return NPA_AF_ERR_PARAM; + + mutex_lock(&rvu->rsrc_lock); + + /* 0 to 63 lfs -> idx 0, 64 - 127 lfs -> idx 1 */ + ridx =3D lf >> 6; + lfmask =3D BIT_ULL(ridx ? lf - NPA_DPC_LFS_PER_REG : lf); + cntr =3D req->cntr_id; + + ridx =3D 2 * cntr + ridx; + + val =3D rvu_read64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx)); + /* Check if the counter is allotted to this LF */ + if (!(val & lfmask)) { + mutex_unlock(&rvu->rsrc_lock); + return 0; + } + + /* Revert permission */ + val &=3D ~lfmask; + rvu_write64(rvu, blkaddr, NPA_AF_DPC_PERMITX(ridx), val); + + /* Free this counter */ + rvu_free_rsrc(&rvu->npa_dpc, req->cntr_id); + + mutex_unlock(&rvu->rsrc_lock); + + return 0; +} + +void npa_cn20k_dpc_free_all(struct rvu *rvu, u16 pcifunc) +{ + struct npa_cn20k_dpc_free_req req; + int i; + + req.hdr.pcifunc =3D pcifunc; + for (i =3D 0; i < NPA_DPC_MAX; i++) { + req.cntr_id =3D i; + npa_cn20k_dpc_free(rvu, &req); + } +} + +int rvu_mbox_handler_npa_cn20k_dpc_free(struct rvu *rvu, + struct npa_cn20k_dpc_free_req *req, + struct msg_rsp *rsp) +{ + if (!is_cn20k(rvu->pdev)) + return -EOPNOTSUPP; + + return npa_cn20k_dpc_free(rvu, req); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h b/driver= s/net/ethernet/marvell/octeontx2/af/cn20k/reg.h index 8bfaa507ee50..9b49e376878e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/reg.h @@ -143,4 +143,11 @@ offset =3D (0xb000000ull | (a) << 4 | (b) << 20); \ offset; }) =20 +/* NPA Registers */ +#define NPA_AF_DPCX_CFG(a) (0x800 | (a) << 6) +#define NPA_AF_DPC_PERMITX(a) (0x1000 | (a) << 3) + +#define NPA_DPC_MAX 32 +#define NPA_DPC_LFS_PER_REG 64 + #endif /* RVU_MBOX_REG_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 4a97bd93d882..b29ec26b66b7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -213,6 +213,10 @@ M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_= aq_enq_rsp) \ M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ M(NPA_CN20K_AQ_ENQ, 0x404, npa_cn20k_aq_enq, npa_cn20k_aq_enq_req, \ npa_cn20k_aq_enq_rsp) \ +M(NPA_CN20K_DPC_ALLOC, 0x405, npa_cn20k_dpc_alloc, npa_cn20k_dpc_alloc_req= , \ + npa_cn20k_dpc_alloc_rsp) \ +M(NPA_CN20K_DPC_FREE, 0x406, npa_cn20k_dpc_free, npa_cn20k_dpc_free_req, \ + msg_rsp) \ /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ @@ -910,6 +914,21 @@ struct npa_cn20k_aq_enq_rsp { }; }; =20 +struct npa_cn20k_dpc_alloc_req { + struct mbox_msghdr hdr; + u16 dpc_conf; +}; + +struct npa_cn20k_dpc_alloc_rsp { + struct mbox_msghdr hdr; + u8 cntr_id; +}; + +struct npa_cn20k_dpc_free_req { + struct mbox_msghdr hdr; + u8 cntr_id; +}; + /* Disable all contexts of type 'ctype' */ struct hwctx_disable_req { struct mbox_msghdr hdr; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 0c4dae6d0967..90ad2c138898 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -663,6 +663,9 @@ struct rvu { /* CPT interrupt lock */ spinlock_t cpt_intr_lock; =20 + /* NPA */ + struct rsrc_bmap npa_dpc; + struct mutex mbox_lock; /* Serialize mbox up and down msgs */ u16 rep_pcifunc; bool altaf_ready; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npa.c index d15e6969ee56..30c067399660 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c @@ -8,6 +8,8 @@ #include #include =20 +#include "cn20k/api.h" +#include "cn20k/reg.h" #include "rvu_struct.h" #include "rvu_reg.h" #include "rvu.h" @@ -494,6 +496,8 @@ int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struc= t msg_req *req, return NPA_AF_ERR_LF_RESET; } =20 + if (is_cn20k(rvu->pdev)) + npa_cn20k_dpc_free_all(rvu, pcifunc); npa_ctx_free(rvu, pfvf); =20 return 0; @@ -559,12 +563,19 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_bl= ock *block) int rvu_npa_init(struct rvu *rvu) { struct rvu_hwinfo *hw =3D rvu->hw; - int blkaddr; + int err, blkaddr; =20 blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); if (blkaddr < 0) return 0; =20 + if (is_cn20k(rvu->pdev)) { + rvu->npa_dpc.max =3D NPA_DPC_MAX; + err =3D rvu_alloc_bitmap(&rvu->npa_dpc); + if (err) + return err; + } + /* Initialize admin queue */ return npa_aq_init(rvu, &hw->block[blkaddr]); } @@ -581,6 +592,9 @@ void rvu_npa_freemem(struct rvu *rvu) =20 block =3D &hw->block[blkaddr]; rvu_aq_free(rvu, block->aq); + + if (is_cn20k(rvu->pdev)) + kfree(rvu->npa_dpc.bmap); } =20 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf) @@ -601,6 +615,7 @@ void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, = int npalf) if (is_cn20k(rvu->pdev)) { ctx_req.ctype =3D NPA_AQ_CTYPE_HALO; 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charset="utf-8" From: Linu Cherian Similar to other hardware contexts add debugfs support for unified Halo context. Sample output on cn20k:: /sys/kernel/debug/cn20k/npa # cat halo_ctx =3D=3D=3D=3D=3D=3Dhalo : 2=3D=3D=3D=3D=3D=3D=3D W0: Stack base ffffff790000 W1: ena 1 W1: nat_align 0 W1: stack_caching 1 W1: aura drop ena 0 W1: aura drop 0 W1: buf_offset 0 W1: buf_size 32 W1: ref_cnt_prof 0 W2: stack_max_pages 13 W2: stack_pages 11 W3: bp_0 0 W3: bp_1 0 W3: bp_2 0 snip .. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../marvell/octeontx2/af/cn20k/debugfs.c | 60 ++++++++++++++++ .../marvell/octeontx2/af/cn20k/debugfs.h | 2 + .../marvell/octeontx2/af/rvu_debugfs.c | 71 ++++++++++++++++--- 3 files changed, 125 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c index 6f13296303cb..22c2bd32188d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.c @@ -476,3 +476,63 @@ void print_npa_cn20k_pool_ctx(struct seq_file *m, pool->thresh_qint_idx, pool->err_qint_idx); seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst); } + +void print_npa_cn20k_halo_ctx(struct seq_file *m, struct npa_aq_enq_rsp *r= sp) +{ + struct npa_cn20k_aq_enq_rsp *cn20k_rsp; + struct npa_cn20k_halo_s *halo; + + cn20k_rsp =3D (struct npa_cn20k_aq_enq_rsp *)rsp; + halo =3D &cn20k_rsp->halo; + + seq_printf(m, "W0: Stack base\t\t%llx\n", halo->stack_base); + + seq_printf(m, "W1: ena \t\t%d\nW1: nat_align \t\t%d\n", + halo->ena, halo->nat_align); + seq_printf(m, "W1: stack_caching\t%d\n", + halo->stack_caching); + seq_printf(m, "W1: aura drop ena\t%d\n", halo->aura_drop_ena); + seq_printf(m, "W1: aura drop\t\t%d\n", halo->aura_drop); + seq_printf(m, "W1: buf_offset\t\t%d\nW1: buf_size\t\t%d\n", + halo->buf_offset, halo->buf_size); + seq_printf(m, "W1: ref_cnt_prof\t\t%d\n", halo->ref_cnt_prof); + seq_printf(m, "W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", + halo->stack_max_pages, halo->stack_pages); + seq_printf(m, "W3: bp_0\t\t%d\nW3: bp_1\t\t%d\nW3: bp_2\t\t%d\n", + halo->bp_0, halo->bp_1, halo->bp_2); + seq_printf(m, "W3: bp_3\t\t%d\nW3: bp_4\t\t%d\nW3: bp_5\t\t%d\n", + halo->bp_3, halo->bp_4, halo->bp_5); + seq_printf(m, "W3: bp_6\t\t%d\nW3: bp_7\t\t%d\nW3: bp_ena_0\t\t%d\n", + halo->bp_6, halo->bp_7, halo->bp_ena_0); + seq_printf(m, "W3: bp_ena_1\t\t%d\nW3: bp_ena_2\t\t%d\n", + halo->bp_ena_1, halo->bp_ena_2); + seq_printf(m, "W3: bp_ena_3\t\t%d\nW3: bp_ena_4\t\t%d\n", + halo->bp_ena_3, halo->bp_ena_4); + seq_printf(m, "W3: bp_ena_5\t\t%d\nW3: bp_ena_6\t\t%d\n", + halo->bp_ena_5, halo->bp_ena_6); + seq_printf(m, "W3: bp_ena_7\t\t%d\n", halo->bp_ena_7); + seq_printf(m, "W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d= \n", + halo->stack_offset, halo->shift, halo->avg_level); + seq_printf(m, "W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d\n= ", + halo->avg_con, halo->fc_ena, halo->fc_stype); + seq_printf(m, "W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d\n", + halo->fc_hyst_bits, halo->fc_up_crossing); + seq_printf(m, "W4: update_time\t\t%d\n", halo->update_time); + seq_printf(m, "W5: fc_addr\t\t%llx\n", halo->fc_addr); + seq_printf(m, "W6: ptr_start\t\t%llx\n", halo->ptr_start); + seq_printf(m, "W7: ptr_end\t\t%llx\n", halo->ptr_end); + seq_printf(m, "W8: bpid_0\t\t%d\n", halo->bpid_0); + seq_printf(m, "W8: err_int \t\t%d\nW8: err_int_ena\t\t%d\n", + halo->err_int, halo->err_int_ena); + seq_printf(m, "W8: thresh_int\t\t%d\nW8: thresh_int_ena \t%d\n", + halo->thresh_int, halo->thresh_int_ena); + seq_printf(m, "W8: thresh_up\t\t%d\nW8: thresh_qint_idx\t%d\n", + halo->thresh_up, halo->thresh_qint_idx); + seq_printf(m, "W8: err_qint_idx \t%d\n", halo->err_qint_idx); + seq_printf(m, "W9: thresh\t\t%llu\n", (u64)halo->thresh); + seq_printf(m, "W9: fc_msh_dst\t\t%d\n", halo->fc_msh_dst); + seq_printf(m, "W9: op_dpc_ena\t\t%d\nW9: op_dpc_set\t\t%d\n", + halo->op_dpc_ena, halo->op_dpc_set); + seq_printf(m, "W9: stream_ctx\t\t%d\nW9: unified_ctx\t\t%d\n", + halo->stream_ctx, halo->unified_ctx); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h b/dr= ivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h index 0c5f05883666..7e00c7499e35 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/debugfs.h @@ -27,5 +27,7 @@ void print_npa_cn20k_aura_ctx(struct seq_file *m, struct npa_cn20k_aq_enq_rsp *rsp); void print_npa_cn20k_pool_ctx(struct seq_file *m, struct npa_cn20k_aq_enq_rsp *rsp); +void print_npa_cn20k_halo_ctx(struct seq_file *m, + struct npa_aq_enq_rsp *rsp); =20 #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index fa461489acdd..0ac59103b4a4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -968,6 +968,9 @@ static void print_npa_qsize(struct seq_file *m, struct = rvu_pfvf *pfvf) seq_printf(m, "Aura count : %d\n", pfvf->aura_ctx->qsize); seq_printf(m, "Aura context ena/dis bitmap : %*pb\n", pfvf->aura_ctx->qsize, pfvf->aura_bmap); + if (pfvf->halo_bmap) + seq_printf(m, "Halo context ena/dis bitmap : %*pb\n", + pfvf->aura_ctx->qsize, pfvf->halo_bmap); } =20 if (!pfvf->pool_ctx) { @@ -1195,6 +1198,20 @@ static void print_npa_pool_ctx(struct seq_file *m, s= truct npa_aq_enq_rsp *rsp) seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst); } =20 +static const char *npa_ctype_str(int ctype) +{ + switch (ctype) { + case NPA_AQ_CTYPE_AURA: + return "aura"; + case NPA_AQ_CTYPE_HALO: + return "halo"; + case NPA_AQ_CTYPE_POOL: + return "pool"; + default: + return "unknown"; + } +} + /* Reads aura/pool's ctx from admin queue */ static int rvu_dbg_npa_ctx_display(struct seq_file *m, void *unused, int c= type) { @@ -1211,6 +1228,7 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) =20 switch (ctype) { case NPA_AQ_CTYPE_AURA: + case NPA_AQ_CTYPE_HALO: npalf =3D rvu->rvu_dbg.npa_aura_ctx.lf; id =3D rvu->rvu_dbg.npa_aura_ctx.id; all =3D rvu->rvu_dbg.npa_aura_ctx.all; @@ -1235,6 +1253,9 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) } else if (ctype =3D=3D NPA_AQ_CTYPE_POOL && !pfvf->pool_ctx) { seq_puts(m, "Pool context is not initialized\n"); return -EINVAL; + } else if (ctype =3D=3D NPA_AQ_CTYPE_HALO && !pfvf->aura_ctx) { + seq_puts(m, "Halo context is not initialized\n"); + return -EINVAL; } =20 memset(&aq_req, 0, sizeof(struct npa_aq_enq_req)); @@ -1244,6 +1265,9 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) if (ctype =3D=3D NPA_AQ_CTYPE_AURA) { max_id =3D pfvf->aura_ctx->qsize; print_npa_ctx =3D print_npa_aura_ctx; + } else if (ctype =3D=3D NPA_AQ_CTYPE_HALO) { + max_id =3D pfvf->aura_ctx->qsize; + print_npa_ctx =3D print_npa_cn20k_halo_ctx; } else { max_id =3D pfvf->pool_ctx->qsize; print_npa_ctx =3D print_npa_pool_ctx; @@ -1251,8 +1275,7 @@ static int rvu_dbg_npa_ctx_display(struct seq_file *m= , void *unused, int ctype) =20 if (id < 0 || id >=3D max_id) { seq_printf(m, "Invalid %s, valid range is 0-%d\n", - (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? "aura" : "pool", - max_id - 1); + npa_ctype_str(ctype), max_id - 1); return -EINVAL; } =20 @@ -1265,12 +1288,19 @@ static int rvu_dbg_npa_ctx_display(struct seq_file = *m, void *unused, int ctype) aq_req.aura_id =3D aura; =20 /* Skip if queue is uninitialized */ + if (ctype =3D=3D NPA_AQ_CTYPE_AURA && + !test_bit(aura, pfvf->aura_bmap)) + continue; + + if (ctype =3D=3D NPA_AQ_CTYPE_HALO && + !test_bit(aura, pfvf->halo_bmap)) + continue; + if (ctype =3D=3D NPA_AQ_CTYPE_POOL && !test_bit(aura, pfvf->pool_bmap)) continue; =20 - seq_printf(m, "=3D=3D=3D=3D=3D=3D%s : %d=3D=3D=3D=3D=3D=3D=3D\n", - (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? "AURA" : "POOL", - aq_req.aura_id); + seq_printf(m, "=3D=3D=3D=3D=3D=3D%s : %d=3D=3D=3D=3D=3D=3D=3D\n", npa_ct= ype_str(ctype), + aq_req.aura_id); rc =3D rvu_npa_aq_enq_inst(rvu, &aq_req, &rsp); if (rc) { seq_puts(m, "Failed to read context\n"); @@ -1299,6 +1329,12 @@ static int write_npa_ctx(struct rvu *rvu, bool all, return -EINVAL; } max_id =3D pfvf->aura_ctx->qsize; + } else if (ctype =3D=3D NPA_AQ_CTYPE_HALO) { + if (!pfvf->aura_ctx) { + dev_warn(rvu->dev, "Halo context is not initialized\n"); + return -EINVAL; + } + max_id =3D pfvf->aura_ctx->qsize; } else if (ctype =3D=3D NPA_AQ_CTYPE_POOL) { if (!pfvf->pool_ctx) { dev_warn(rvu->dev, "Pool context is not initialized\n"); @@ -1309,13 +1345,14 @@ static int write_npa_ctx(struct rvu *rvu, bool all, =20 if (id < 0 || id >=3D max_id) { dev_warn(rvu->dev, "Invalid %s, valid range is 0-%d\n", - (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? "aura" : "pool", + npa_ctype_str(ctype), max_id - 1); return -EINVAL; } =20 switch (ctype) { case NPA_AQ_CTYPE_AURA: + case NPA_AQ_CTYPE_HALO: rvu->rvu_dbg.npa_aura_ctx.lf =3D npalf; rvu->rvu_dbg.npa_aura_ctx.id =3D id; rvu->rvu_dbg.npa_aura_ctx.all =3D all; @@ -1374,12 +1411,12 @@ static ssize_t rvu_dbg_npa_ctx_write(struct file *f= ilp, const char __user *buffer, size_t count, loff_t *ppos, int ctype) { - char *cmd_buf, *ctype_string =3D (ctype =3D=3D NPA_AQ_CTYPE_AURA) ? - "aura" : "pool"; + const char *ctype_string =3D npa_ctype_str(ctype); struct seq_file *seqfp =3D filp->private_data; struct rvu *rvu =3D seqfp->private; int npalf, id =3D 0, ret; bool all =3D false; + char *cmd_buf; =20 if ((*ppos !=3D 0) || !count) return -EINVAL; @@ -1417,6 +1454,21 @@ static int rvu_dbg_npa_aura_ctx_display(struct seq_f= ile *filp, void *unused) =20 RVU_DEBUG_SEQ_FOPS(npa_aura_ctx, npa_aura_ctx_display, npa_aura_ctx_write); =20 +static ssize_t rvu_dbg_npa_halo_ctx_write(struct file *filp, + const char __user *buffer, + size_t count, loff_t *ppos) +{ + return rvu_dbg_npa_ctx_write(filp, buffer, count, ppos, + NPA_AQ_CTYPE_HALO); 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charset="utf-8" Use unified Halo context present in CN20K hardware for octeontx2 netdevs instead of aura and pool contexts. Note that with this halo context in place RQ backpressure is not being configured and the same will be supported later. Signed-off-by: Subbaraya Sundeep --- .../ethernet/marvell/octeontx2/nic/cn20k.c | 209 +++++++++--------- .../ethernet/marvell/octeontx2/nic/cn20k.h | 3 + .../marvell/octeontx2/nic/otx2_common.h | 3 + .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 8 + 4 files changed, 120 insertions(+), 103 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn20k.c index dbf173196608..721721dc1564 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c @@ -242,15 +242,6 @@ int cn20k_register_pfvf_mbox_intr(struct otx2_nic *pf,= int numvfs) =20 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full= */ =20 -static u8 cn20k_aura_bpid_idx(struct otx2_nic *pfvf, int aura_id) -{ -#ifdef CONFIG_DCB - return pfvf->queue_to_pfc_map[aura_id]; -#else - return 0; -#endif -} - static int cn20k_tc_get_entry_index(struct otx2_flow_config *flow_cfg, struct otx2_tc_flow *node) { @@ -517,15 +508,22 @@ int cn20k_tc_alloc_entry(struct otx2_nic *nic, return 0; } =20 -static int cn20k_aura_aq_init(struct otx2_nic *pfvf, int aura_id, - int pool_id, int numptrs) +static int cn20k_halo_aq_init(struct otx2_nic *pfvf, u16 pool_id, + int stack_pages, int numptrs, int buf_size, + int type) { + struct page_pool_params pp_params =3D { 0 }; struct npa_cn20k_aq_enq_req *aq; struct otx2_pool *pool; - u8 bpid_idx; - int err; + struct page_pool *pp; + int err, sz; =20 pool =3D &pfvf->qset.pool[pool_id]; + /* Alloc memory for stack which is used to store buffer pointers */ + err =3D qmem_alloc(pfvf->dev, &pool->stack, + stack_pages, pfvf->hw.stack_pg_bytes); + if (err) + return err; =20 /* Allocate memory for HW to update Aura count. * Alloc one cache line, so that it fits all FC_STYPE modes. @@ -536,6 +534,8 @@ static int cn20k_aura_aq_init(struct otx2_nic *pfvf, in= t aura_id, return err; } =20 + pool->rbsize =3D buf_size; + /* Initialize this aura's context via AF */ aq =3D otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox); if (!aq) { @@ -548,49 +548,60 @@ static int cn20k_aura_aq_init(struct otx2_nic *pfvf, = int aura_id, return -ENOMEM; } =20 - aq->aura_id =3D aura_id; - - /* Will be filled by AF with correct pool context address */ - aq->aura.pool_addr =3D pool_id; - aq->aura.pool_caching =3D 1; - aq->aura.shift =3D ilog2(numptrs) - 8; - aq->aura.count =3D numptrs; - aq->aura.limit =3D numptrs; - aq->aura.avg_level =3D 255; - aq->aura.ena =3D 1; - aq->aura.fc_ena =3D 1; - aq->aura.fc_addr =3D pool->fc_addr->iova; - aq->aura.fc_hyst_bits =3D 0; /* Store count on all updates */ - - /* Enable backpressure for RQ aura */ - if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { - aq->aura.bp_ena =3D 0; - /* If NIX1 LF is attached then specify NIX1_RX. - * - * Below NPA_AURA_S[BP_ENA] is set according to the - * NPA_BPINTF_E enumeration given as: - * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so - * NIX0_RX is 0x0 + 0*0x1 =3D 0 - * NIX1_RX is 0x0 + 1*0x1 =3D 1 - * But in HRM it is given that - * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to - * NIX-RX based on [BP] level. One bit per NIX-RX; index - * enumerated by NPA_BPINTF_E." - */ - if (pfvf->nix_blkaddr =3D=3D BLKADDR_NIX1) - aq->aura.bp_ena =3D 1; - - bpid_idx =3D cn20k_aura_bpid_idx(pfvf, aura_id); - aq->aura.bpid =3D pfvf->bpid[bpid_idx]; + aq->aura_id =3D pool_id; =20 - /* Set backpressure level for RQ's Aura */ - aq->aura.bp =3D RQ_BP_LVL_AURA; + aq->halo.stack_base =3D pool->stack->iova; + aq->halo.stack_caching =3D 1; + aq->halo.ena =3D 1; + aq->halo.buf_size =3D buf_size / 128; + aq->halo.stack_max_pages =3D stack_pages; + aq->halo.shift =3D ilog2(numptrs) - 8; + aq->halo.ptr_start =3D 0; + aq->halo.ptr_end =3D ~0ULL; + + aq->halo.avg_level =3D 255; + aq->halo.fc_ena =3D 1; + aq->halo.fc_addr =3D pool->fc_addr->iova; + aq->halo.fc_hyst_bits =3D 0; /* Store count on all updates */ + + if (pfvf->npa_dpc_valid) { + aq->halo.op_dpc_ena =3D 1; + aq->halo.op_dpc_set =3D pfvf->npa_dpc; } + aq->halo.unified_ctx =3D 1; =20 /* Fill AQ info */ - aq->ctype =3D NPA_AQ_CTYPE_AURA; + aq->ctype =3D NPA_AQ_CTYPE_HALO; aq->op =3D NPA_AQ_INSTOP_INIT; =20 + if (type !=3D AURA_NIX_RQ) { + pool->page_pool =3D NULL; + return 0; + } + + sz =3D ALIGN(ALIGN(SKB_DATA_ALIGN(buf_size), OTX2_ALIGN), PAGE_SIZE); + pp_params.order =3D get_order(sz); + pp_params.flags =3D PP_FLAG_DMA_MAP; + pp_params.pool_size =3D min(OTX2_PAGE_POOL_SZ, numptrs); + pp_params.nid =3D NUMA_NO_NODE; + pp_params.dev =3D pfvf->dev; + pp_params.dma_dir =3D DMA_FROM_DEVICE; + + pp =3D page_pool_create(&pp_params); + if (IS_ERR(pp)) { + netdev_err(pfvf->netdev, "Creation of page pool failed\n"); + pool->page_pool =3D NULL; + return PTR_ERR(pp); + } + + pool->page_pool =3D pp; + + return 0; +} + +static int cn20k_aura_aq_init(struct otx2_nic *pfvf, int aura_id, + int pool_id, int numptrs) +{ return 0; } =20 @@ -598,71 +609,63 @@ static int cn20k_pool_aq_init(struct otx2_nic *pfvf, = u16 pool_id, int stack_pages, int numptrs, int buf_size, int type) { - struct page_pool_params pp_params =3D { 0 }; - struct npa_cn20k_aq_enq_req *aq; - struct otx2_pool *pool; - int err, sz; + return cn20k_halo_aq_init(pfvf, pool_id, stack_pages, + numptrs, buf_size, type); +} =20 - pool =3D &pfvf->qset.pool[pool_id]; - /* Alloc memory for stack which is used to store buffer pointers */ - err =3D qmem_alloc(pfvf->dev, &pool->stack, - stack_pages, pfvf->hw.stack_pg_bytes); +int cn20k_npa_alloc_dpc(struct otx2_nic *nic) +{ + struct npa_cn20k_dpc_alloc_req *req; + struct npa_cn20k_dpc_alloc_rsp *rsp; + int err; + + req =3D otx2_mbox_alloc_msg_npa_cn20k_dpc_alloc(&nic->mbox); + if (!req) + return -ENOMEM; + + /* Count successful ALLOC requests only */ + req->dpc_conf =3D 1ULL << 4; + + err =3D otx2_sync_mbox_msg(&nic->mbox); if (err) return err; =20 - pool->rbsize =3D buf_size; + rsp =3D (struct npa_cn20k_dpc_alloc_rsp *)otx2_mbox_get_rsp(&nic->mbox.mb= ox, + 0, &req->hdr); + if (IS_ERR(rsp)) + return PTR_ERR(rsp); =20 - /* Initialize this pool's context via AF */ - aq =3D otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox); - if (!aq) { - /* Shared mbox memory buffer is full, flush it and retry */ - err =3D otx2_sync_mbox_msg(&pfvf->mbox); - if (err) { - qmem_free(pfvf->dev, pool->stack); - pool->stack =3D NULL; - return err; - } - aq =3D otx2_mbox_alloc_msg_npa_cn20k_aq_enq(&pfvf->mbox); - if (!aq) { - qmem_free(pfvf->dev, pool->stack); - pool->stack =3D NULL; - return -ENOMEM; - } - } + nic->npa_dpc =3D rsp->cntr_id; + nic->npa_dpc_valid =3D true; =20 - aq->aura_id =3D pool_id; - aq->pool.stack_base =3D pool->stack->iova; - aq->pool.stack_caching =3D 1; - aq->pool.ena =3D 1; - aq->pool.buf_size =3D buf_size / 128; - aq->pool.stack_max_pages =3D stack_pages; - aq->pool.shift =3D ilog2(numptrs) - 8; - aq->pool.ptr_start =3D 0; - aq->pool.ptr_end =3D ~0ULL; + return 0; +} =20 - /* Fill AQ info */ - aq->ctype =3D NPA_AQ_CTYPE_POOL; - aq->op =3D NPA_AQ_INSTOP_INIT; +int cn20k_npa_free_dpc(struct otx2_nic *nic) +{ + struct npa_cn20k_dpc_free_req *req; + int err; =20 - if (type !=3D AURA_NIX_RQ) { - pool->page_pool =3D NULL; + if (!nic->npa_dpc_valid) return 0; - } =20 - sz =3D ALIGN(ALIGN(SKB_DATA_ALIGN(buf_size), OTX2_ALIGN), PAGE_SIZE); - pp_params.order =3D get_order(sz); - pp_params.flags =3D PP_FLAG_DMA_MAP; - pp_params.pool_size =3D min(OTX2_PAGE_POOL_SZ, numptrs); - pp_params.nid =3D NUMA_NO_NODE; - pp_params.dev =3D pfvf->dev; - pp_params.dma_dir =3D DMA_FROM_DEVICE; - pool->page_pool =3D page_pool_create(&pp_params); - if (IS_ERR(pool->page_pool)) { - netdev_err(pfvf->netdev, "Creation of page pool failed\n"); - return PTR_ERR(pool->page_pool); + mutex_lock(&nic->mbox.lock); + + req =3D otx2_mbox_alloc_msg_npa_cn20k_dpc_free(&nic->mbox); + if (!req) { + mutex_unlock(&nic->mbox.lock); + return -ENOMEM; } =20 - return 0; + req->cntr_id =3D nic->npa_dpc; + + err =3D otx2_sync_mbox_msg(&nic->mbox); + if (!err) + nic->npa_dpc_valid =3D false; + + mutex_unlock(&nic->mbox.lock); + + return err; } =20 static int cn20k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_a= ura) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn20k.h index b5e527f6d7eb..16a69d84ea79 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn20k.h @@ -28,4 +28,7 @@ int cn20k_tc_alloc_entry(struct otx2_nic *nic, struct otx2_tc_flow *new_node, struct npc_install_flow_req *dummy); int cn20k_tc_free_mcam_entry(struct otx2_nic *nic, u16 entry); +int cn20k_npa_alloc_dpc(struct otx2_nic *nic); +int cn20k_npa_free_dpc(struct otx2_nic *nic); + #endif /* CN20K_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index eecee612b7b2..f997dfc0fedd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -592,6 +592,9 @@ struct otx2_nic { struct cn10k_ipsec ipsec; /* af_xdp zero-copy */ unsigned long *af_xdp_zc_qidx; + + bool npa_dpc_valid; + u8 npa_dpc; /* NPA DPC counter id */ }; =20 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index ee623476e5ff..2b5fe67d297c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1651,6 +1651,9 @@ int otx2_init_hw_resources(struct otx2_nic *pf) if (!is_otx2_lbkvf(pf->pdev)) otx2_nix_config_bp(pf, true); =20 + if (is_cn20k(pf->pdev)) + cn20k_npa_alloc_dpc(pf); + /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ err =3D otx2_rq_aura_pool_init(pf); if (err) { @@ -1726,6 +1729,8 @@ int otx2_init_hw_resources(struct otx2_nic *pf) otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); otx2_aura_pool_free(pf); err_free_nix_lf: + if (pf->npa_dpc_valid) + cn20k_npa_free_dpc(pf); mutex_lock(&mbox->lock); free_req =3D otx2_mbox_alloc_msg_nix_lf_free(mbox); if (free_req) { @@ -1790,6 +1795,9 @@ void otx2_free_hw_resources(struct otx2_nic *pf) =20 otx2_free_sq_res(pf); =20 + if (is_cn20k(pf->pdev)) + cn20k_npa_free_dpc(pf); + /* Free RQ buffer pointers*/ otx2_free_aura_ptr(pf, AURA_NIX_RQ); =20 --=20 2.48.1