From nobody Mon May 25 00:09:40 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEDC536AB49; Wed, 20 May 2026 08:35:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266108; cv=none; b=JJ5oFaNAH8yTfCZrq6EBCAigl0w0g3aASPWxve8Uj6U47q9hiNjRH2l7c+aklZHfxUKGenw9vNaOCuapU9CZYl9GjDzcUEB+7+JGsb4+liAIBcoy19LNEIIbJGb0NRmIMsTSywiYfgs5CVfNspCNosbI4uaql/gBJ/IF5NdmElI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266108; c=relaxed/simple; bh=c0BQV3QZAglV2BnasZlkY0XT5u6Wys0soTuSxJOdJlc=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=o+BmBP5AuI7LTg/OR65ZlUJihtye79f+PYDub1P6Slr6ztaP/bllhfjo5GqHLdA3c66wozX5b2SW90HTL51D/4Z8qO2SHdJPZu6MIfFjX9g0jf4a0zCOKotdTGR1favkdbO67SkiqFM4+vUYAzIfVTudZL90mWrcSQsKszJll60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BOkD+ZLr; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IvoSBswQ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BOkD+ZLr"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IvoSBswQ" Date: Wed, 20 May 2026 08:35:03 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266105; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=qhFNtE5VUtf+/5wWvBx7AWHQd0D1zpj+/RxzgcGrZiQ=; b=BOkD+ZLrgwd7Obi0zWPZ4DS03CL7vQrHrpxLRLXqKVRQ6YQObYBlHt3W91DGFOkSB/qQG/ wPWLtHczGMadaKVdIgEtVo/B312c/XOtnBvSjCuvfa5K2+ctLzVDy1kfUv1QnDOD13ENgr FHqMx1DZYlwn4pAKBTGpKBv8YLsw/RvIMASbJyyuQLfJttnagoGaKEGQI7B8fIKF+mUhG8 exJtn0wiYr1RMSMb+dZSmXW99wBnTSYY2Ei3BIo+bqJ6+8+0ZAYTqplUUfTGToeChKcqgN nwG7YeZ9UHb/xiDlrasVbQYW+US7in21TU9wmKhqKy6YEqGaxe9wHTtg/01wGA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266105; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=qhFNtE5VUtf+/5wWvBx7AWHQd0D1zpj+/RxzgcGrZiQ=; b=IvoSBswQeGSsrcTznrLgq3lM3J6siQoxO1Dgk1N6Pi8mJfe9zRvwfttUmArLkWtgf9Q/Fe vrhsuxPZ7ItmBaBg== From: "tip-bot2 for Peter Zijlstra" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: sched/core] x86/topology: Add paramter to split LLC Cc: "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926610392.711.16598862973685343682.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the sched/core branch of tip: Commit-ID: abb12b9b52cfe272c03a859b43a658f0d9cbf285 Gitweb: https://git.kernel.org/tip/abb12b9b52cfe272c03a859b43a658f0d= 9cbf285 Author: Peter Zijlstra AuthorDate: Thu, 19 Feb 2026 12:11:16 +01:00 Committer: Peter Zijlstra CommitterDate: Thu, 09 Apr 2026 15:49:46 +02:00 x86/topology: Add paramter to split LLC Add a (debug) option to virtually split the LLC, no CAT involved, just fake topology. Used to test code that depends (either in behaviour or directly) = on there being multiple LLC domains in a node. Signed-off-by: Peter Zijlstra (Intel) --- Documentation/admin-guide/kernel-parameters.txt | 12 ++++++++++- arch/x86/include/asm/processor.h | 5 ++++- arch/x86/kernel/smpboot.c | 20 ++++++++++++++++- 3 files changed, 37 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 03a5506..a2161f6 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -7254,6 +7254,18 @@ Kernel parameters Not specifying this option is equivalent to spec_store_bypass_disable=3Dauto. =20 + split_llc=3D + [X86,EARLY] Split the LLC N-ways + + When set, the LLC is split this many ways by matching + 'core_id % n'. This is setup before SMP bringup and + used during SMP bringup before it knows the full + topology. If your core count doesn't nicely divide by + the number given, you get to keep the pieces. + + This is mostly a debug feature to emulate multiple LLCs + on hardware that only have a single LLC. + split_lock_detect=3D [X86] Enable split lock detection or bus lock detection =20 diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index a24c780..d0d7cef 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -699,6 +699,11 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu) return per_cpu(cpu_info.topo.l2c_id, cpu); } =20 +static inline u32 per_cpu_core_id(unsigned int cpu) +{ + return per_cpu(cpu_info.topo.core_id, cpu); +} + #ifdef CONFIG_CPU_SUP_AMD /* * Issue a DIV 0/1 insn to clear any division data from previous DIV diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 294a8ea..cb999fe 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -424,6 +424,21 @@ static const struct x86_cpu_id intel_cod_cpu[] =3D { {} }; =20 +/* + * Allows splitting the LLC by matching 'core_id % split_llc'. + * + * This is mostly a debug hack to emulate systems with multiple LLCs per n= ode + * on systems that do not naturally have this. + */ +static unsigned int split_llc =3D 0; + +static int __init split_llc_setup(char *str) +{ + get_option(&str, &split_llc); + return 0; +} +early_param("split_llc", split_llc_setup); + static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) { const struct x86_cpu_id *id =3D x86_match_cpu(intel_cod_cpu); @@ -438,6 +453,11 @@ static bool match_llc(struct cpuinfo_x86 *c, struct cp= uinfo_x86 *o) if (per_cpu_llc_id(cpu1) !=3D per_cpu_llc_id(cpu2)) return false; =20 + if (split_llc && + (per_cpu_core_id(cpu1) % split_llc) !=3D + (per_cpu_core_id(cpu2) % split_llc)) + return false; + /* * Allow the SNC topology without warning. Return of false * means 'c' does not share the LLC of 'o'. This will be