From nobody Mon May 25 00:09:52 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 858C93DB312; Wed, 20 May 2026 08:34:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266081; cv=none; b=GMqjbk2Rfs1wYK3LJ48Z5TzSVQU3kD8JVVbwsXs+ncShuwvL6byR13RLMTkWXB7dZaANihoPzq7Ljcg5jdpn8+rjvtwmdkQjg9uWRg+jjhyNin+zM+XT7igACn/Lbecr43ZvXn/cMhLUzv7rKHIXX40ScuxIWLaFp6JzW0s0O4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266081; c=relaxed/simple; bh=Ry2xqWvURfenXce25SVVTQ6G69IJ7NvPSBkbzm1/Mc8=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Mnpi6maMcEqE6rn2pphFxWkiecdQDK4JxjRxgERykD1KzU/QI70ou0VoQdi9v/icVwD3Z3yG/GQMYv8Zt0n9I8vtp8YYhBkPaIgK9HFIscAPUVBmMUu+rUXmBK4W40Rg6Y6IIchvQ9kP90areyYvnjL7Bm1x4Q/OOAH3TbCarHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PEpSrrgu; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mqpq0xI3; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PEpSrrgu"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mqpq0xI3" Date: Wed, 20 May 2026 08:34:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266079; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=59VsgSEjLKiWA5AjikhIVOZl3OmPpxft5Co98v/z2I8=; b=PEpSrrguMt+Zr/a/sDKYXfYcXAL/6C++At6mQ8j8q4CMaJ4FahX8tAhYuEQQLIVH87mbeK oZf3AuS20QHVA05QqiYfavHkGaLaevaj/FbaJ89nNNaH7AZpL6TdPpN0o9qhmxDjqqTw+4 EsfLTMvICxdKQzULTH2rvLOWahj5rpRBXQHnlyoMFCgBbiTwUUGUY1u7uFRcWckUlYmp8c w17NxOrqXHK6f3jryNxc3daNOMeCuBuameVtj1cNhv1uoAUBMpOqaDNVfWDNHu227n0eem ODaaRhVVPbzaqYNVE2m5xC30eYMkA0F6XepUcs9/Jmr7qNJe3E7qRM39IqGfnQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266079; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=59VsgSEjLKiWA5AjikhIVOZl3OmPpxft5Co98v/z2I8=; b=mqpq0xI3E+cfSXf3xhiH0QH+N8zLHHlvuw2qKg1rcZYDggOopTntgG41xul87j/MFvWTQL ocwVLaOAz+bK4PAg== From: "tip-bot2 for Chen Yu" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: sched/core] sched/cache: Skip cache-aware scheduling for single-threaded processes Cc: Chen Yu , Tim Chen , "Peter Zijlstra (Intel)" , Tingyin Duan , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: =?utf-8?q?=3C8a59a13aa58fdb48e410ecb2aabd97fe3ea5d256=2E1778703?= =?utf-8?q?694=2Egit=2Etim=2Ec=2Echen=40linux=2Eintel=2Ecom=3E?= References: =?utf-8?q?=3C8a59a13aa58fdb48e410ecb2aabd97fe3ea5d256=2E17787036?= =?utf-8?q?94=2Egit=2Etim=2Ec=2Echen=40linux=2Eintel=2Ecom=3E?= Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926607795.711.10875717137781285961.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the sched/core branch of tip: Commit-ID: 7b34bb1ca324451c84c0a69136ce92e7928cf72b Gitweb: https://git.kernel.org/tip/7b34bb1ca324451c84c0a69136ce92e79= 28cf72b Author: Chen Yu AuthorDate: Wed, 13 May 2026 13:39:14 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 18 May 2026 21:33:14 +02:00 sched/cache: Skip cache-aware scheduling for single-threaded processes For a single thread, the current wakeup path tends to place it on the same LLC where it was previously running with cache-hot data. There is no need to enable cache-aware scheduling for single-threaded processes for the following reasons: 1. Cache-aware scheduling primarily benefits multi-threaded processes where threads share data. Single-threaded processes typically have no inter-thread data sharing and thus gain little. 2. Enabling it incurs the additional overhead of tracking the thread's residency in the LLCs. 3. Bypassing single-threaded processes avoids excessive concentration of such tasks on a single LLC. Nevertheless, this check can be omitted if users explicitly provide hints for such single-threaded workloads where different processes have shared memory, e.g., via prctl() or other interfaces to be added in the future. Signed-off-by: Chen Yu Co-developed-by: Tim Chen Signed-off-by: Tim Chen Signed-off-by: Peter Zijlstra (Intel) Tested-by: Tingyin Duan Link: https://patch.msgid.link/8a59a13aa58fdb48e410ecb2aabd97fe3ea5d256.177= 8703694.git.tim.c.chen@linux.intel.com --- kernel/sched/fair.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 808f614..df21366 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -1384,8 +1384,12 @@ static int llc_id(int cpu) return per_cpu(sd_llc_id, cpu); } =20 -static bool invalid_llc_nr(struct mm_struct *mm, int cpu) +static bool invalid_llc_nr(struct mm_struct *mm, struct task_struct *p, + int cpu) { + if (get_nr_threads(p) <=3D 1) + return true; + return !fits_capacity((mm->sc_stat.nr_running_avg * cpu_smt_num_threads), per_cpu(sd_llc_size, cpu)); } @@ -1581,7 +1585,7 @@ void account_mm_sched(struct rq *rq, struct task_stru= ct *p, s64 delta_exec) * its preferred state. */ if (epoch - READ_ONCE(mm->sc_stat.epoch) > EPOCH_LLC_AFFINITY_TIMEOUT || - invalid_llc_nr(mm, cpu_of(rq))) { + invalid_llc_nr(mm, p, cpu_of(rq))) { if (mm->sc_stat.cpu !=3D -1) mm->sc_stat.cpu =3D -1; } @@ -1687,9 +1691,9 @@ static inline void update_avg_scale(u64 *avg, u64 sam= ple) =20 static void task_cache_work(struct callback_head *work) { + int cpu, m_a_cpu =3D -1, nr_running =3D 0, curr_cpu; unsigned long next_scan, now =3D jiffies; struct task_struct *p =3D current, *cur; - int cpu, m_a_cpu =3D -1, nr_running =3D 0; unsigned long curr_m_a_occ =3D 0; struct mm_struct *mm =3D p->mm; unsigned long m_a_occ =3D 0; @@ -1711,6 +1715,14 @@ static void task_cache_work(struct callback_head *wo= rk) now + EPOCH_PERIOD)) return; =20 + curr_cpu =3D task_cpu(p); + if (invalid_llc_nr(mm, p, curr_cpu)) { + if (mm->sc_stat.cpu !=3D -1) + mm->sc_stat.cpu =3D -1; + + return; + } + if (!zalloc_cpumask_var(&cpus, GFP_KERNEL)) return; =20 @@ -10326,7 +10338,7 @@ static enum llc_mig can_migrate_llc_task(int src_cp= u, int dst_cpu, return mig_unrestricted; =20 /* skip cache aware load balance for too many threads */ - if (invalid_llc_nr(mm, dst_cpu)) { + if (invalid_llc_nr(mm, p, dst_cpu)) { if (mm->sc_stat.cpu !=3D -1) mm->sc_stat.cpu =3D -1; return mig_unrestricted;