From nobody Mon May 25 00:09:41 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8933F3D5663; Wed, 20 May 2026 08:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266071; cv=none; b=SOSO8lWttpmEKwebGKaTwBUOwrq/Lvrwqwx9WZ2RzbuItwZA74rhH3NbE50791lDWUPF5pzy2cfZpQKp/fbTaAyTsVIzBKxIFYeNyu1JD9MUaj4+8kaQpRA8DP7soyiR/1tvRHLEzder+QgFk0f4TV/wrLFkiodOvMgEDy0TJQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266071; c=relaxed/simple; bh=mI0R0LO17YZuHhiNYCXLchSyGpe60dbC+QRm2FHIv9U=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=bqdxP8NzmEnSe/ZhNmG3reJxHjJBGMSNwWEUg/zFqfGl35Hqb/hlYZbZhHHUcypaIHZ6k/Lz7thUy3hFtwRYZZk5kMGGXd0ZeHoesKCyEGIZk2QEP/NbliBZ2pBrU7S5KGrkSoi5KlWWUTiJtVlNu/m5+tj/j7SHmgZAowVs7rY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ps/vMt93; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=o8n+QhRl; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ps/vMt93"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="o8n+QhRl" Date: Wed, 20 May 2026 08:34:25 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266067; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4qkQe8FR5Gq7suqzZP1UydwdOkqgohbS5EAppFWllNw=; b=ps/vMt93llJIJ9edLMsTOlgyjuzjHNKK8ENfxnTCfZib0wjKkVckZ9jI1Anh6k6d0TEZ+W iNX8B+XaAxRtgSpfUNnUQFtNNwR9BGiSHNi9l7EHqa+BjHgyjZCuBz4kvHWj/J3kZQEG7Y kFDFiR51QBPfLenmZ33HYBzfWvUH473HPx2NDXdV7bnz/U9FpviHHtLpUZ7YQ3HCNHmSwO yl2oPYCFD84wfzSFUEVo9uHlxxyXDhlPqcL1os1zeI+VmSRlAyo/KExevt1OTxWhuPqIx5 668GBuXjRVFmCaXVWo4XXT10/tj/qECs0EjSE4M1fs2Rl/dKc0ra6ZJ+vEjOLA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266067; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4qkQe8FR5Gq7suqzZP1UydwdOkqgohbS5EAppFWllNw=; b=o8n+QhRl6t8TrA8QO/g1wmVt93x29rrYG68tkFxtp1isfuiEl7RhuFZbEYm5QjAGY/mI48 JTDm2ZDOpM4ZxwDg== From: "tip-bot2 for Chen Yu" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: sched/core] sched/cache: Fix race condition during sched domain rebuild Cc: Chen Yu , Tim Chen , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: =?utf-8?q?=3C9afddf439687f04bb56b46625bd9f153eb8abad5=2E1778703?= =?utf-8?q?694=2Egit=2Etim=2Ec=2Echen=40linux=2Eintel=2Ecom=3E?= References: =?utf-8?q?=3C9afddf439687f04bb56b46625bd9f153eb8abad5=2E17787036?= =?utf-8?q?94=2Egit=2Etim=2Ec=2Echen=40linux=2Eintel=2Ecom=3E?= Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926606591.711.3327537291266404848.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the sched/core branch of tip: Commit-ID: 9f7c745850b4b1b7e4706ae81f04c43f204a6a8d Gitweb: https://git.kernel.org/tip/9f7c745850b4b1b7e4706ae81f04c43f2= 04a6a8d Author: Chen Yu AuthorDate: Wed, 13 May 2026 13:39:23 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 18 May 2026 21:33:17 +02:00 sched/cache: Fix race condition during sched domain rebuild sched_cache_active_set_unlocked() checks hardware support without locks: static void sched_cache_active_set(bool locked) { /* hardware does not support */ if (!static_branch_likely(&sched_cache_present)) { _sched_cache_active_set(false, locked); return; } ... If build_sched_domains() runs concurrently during CPU hotplug, it can disable sched_cache_present under sched_domains_mutex and the CPU hotplug lock. If a debugfs write thread evaluates sched_cache_present as true right before that, and then blocks or gets preempted, it might proceed to enable sched_cache_active after the hardware support has been marked as absent. Make it safer by acquiring cpus_read_lock() and sched_domains_mutex_lock() when the user changes sched_cache_active via debugfs. This bug was reported by sashiko. Fixes: 067a31358143 ("sched/cache: Allow the user space to turn on and off = cache aware scheduling") Signed-off-by: Chen Yu Co-developed-by: Tim Chen Signed-off-by: Tim Chen Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/9afddf439687f04bb56b46625bd9f153eb8abad5.177= 8703694.git.tim.c.chen@linux.intel.com --- kernel/sched/debug.c | 4 +++- kernel/sched/sched.h | 2 +- kernel/sched/topology.c | 43 ++++++++++++++-------------------------- 3 files changed, 20 insertions(+), 29 deletions(-) diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c index fe56953..ed3a0d6 100644 --- a/kernel/sched/debug.c +++ b/kernel/sched/debug.c @@ -224,7 +224,9 @@ sched_cache_enable_write(struct file *filp, const char = __user *ubuf, =20 sysctl_sched_cache_user =3D val; =20 - sched_cache_active_set_unlocked(); + sched_cache_active_set(); + + *ppos +=3D cnt; =20 return cnt; } diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 2740939..45a3b77 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -4083,7 +4083,7 @@ static inline bool sched_cache_enabled(void) return static_branch_unlikely(&sched_cache_active); } =20 -extern void sched_cache_active_set_unlocked(void); +extern void sched_cache_active_set(void); =20 #endif =20 diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 7248a72..c257134 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -917,30 +917,20 @@ err: return false; } =20 -static void _sched_cache_active_set(bool enable, bool locked) -{ - if (enable) { - if (locked) - static_branch_enable_cpuslocked(&sched_cache_active); - else - static_branch_enable(&sched_cache_active); - } else { - if (locked) - static_branch_disable_cpuslocked(&sched_cache_active); - else - static_branch_disable(&sched_cache_active); - } -} - /* * Enable/disable cache aware scheduling according to * user input and the presence of hardware support. */ -static void sched_cache_active_set(bool locked) +static void _sched_cache_active_set(void) { + lockdep_assert_cpus_held(); + lockdep_assert_held(&sched_domains_mutex); + /* hardware does not support */ if (!static_branch_likely(&sched_cache_present)) { - _sched_cache_active_set(false, locked); + static_branch_disable_cpuslocked(&sched_cache_active); + if (sched_debug()) + pr_info("%s: cache aware scheduling not supported on this platform\n", = __func__); return; } =20 @@ -951,24 +941,23 @@ static void sched_cache_active_set(bool locked) * for now. */ if (sysctl_sched_cache_user) { - _sched_cache_active_set(true, locked); + static_branch_enable_cpuslocked(&sched_cache_active); if (sched_debug()) pr_info("%s: enabling cache aware scheduling\n", __func__); } else { - _sched_cache_active_set(false, locked); + static_branch_disable_cpuslocked(&sched_cache_active); if (sched_debug()) pr_info("%s: disabling cache aware scheduling\n", __func__); } } =20 -static void sched_cache_active_set_locked(void) +void sched_cache_active_set(void) { - return sched_cache_active_set(true); -} - -void sched_cache_active_set_unlocked(void) -{ - return sched_cache_active_set(false); + cpus_read_lock(); + sched_domains_mutex_lock(); + _sched_cache_active_set(); + sched_domains_mutex_unlock(); + cpus_read_unlock(); } =20 /* @@ -3082,7 +3071,7 @@ error: else static_branch_disable_cpuslocked(&sched_cache_present); =20 - sched_cache_active_set_locked(); + _sched_cache_active_set(); #endif __free_domain_allocs(&d, alloc_state, cpu_map); =20