From nobody Mon May 25 00:08:59 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94CDD3D3D1F; Wed, 20 May 2026 08:34:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266069; cv=none; b=aK/u788jWubhbOoSx4c8T46/dMhk8Ft1ueL5xO6BjnRITvOJKggG0kLD0sZKahJs7cT2njR5MytFx3LKcTniy/ztGtIZ3aNK/70w5bIousN4kV52K5mbDWR0Q1ETgJWYt4E+QCLKP2kQ7vLmkwQZM85UfNS93Z3RZ0OGLTCrz6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266069; c=relaxed/simple; bh=hACoXiYGnsdQlWYKlGIUACrChmu0s5HQ3RBVJGitACM=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=tAMNqWuZe0YUJcDbmAx3KzigUvgQsZrHiQ7gEqJcnFW/JwZyV0aiGpHFbpbftmah1asNuDe1Bt5LwefRWgDJZNozx2bJLIQ2DOvJWOhJTnsTrRWeI6YkRy6sfm62bNR3+xsr3IWdYnKOArmgEr6UWpmz5gBtOYnijwhIhCv9iK4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mTftaUtz; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PozyiboA; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mTftaUtz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PozyiboA" Date: Wed, 20 May 2026 08:34:24 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266066; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DMBmqmnWEjfSXOwfzlEPnQ5lFYlfwryVt7mDU+69Iks=; b=mTftaUtzfLaveUBWSep4SpUX5PEwKCqllybDMCNtcjGnNEp+eNhF4znHRc9YxZGIKudQlh 4z8ElTnxtRi74qcRF0Pjwod1Zpio9bZpYwwQI8Y7sA7+qY7PRtfFqbQsfhFwoWkoXlwoqt WHnwyzPaN6pE8P46HiSLg0BRM4ysmDJkN40uvsevFrZIiL3xpmWDj6uX5cxyPe9wkfzQax izmxpRt13n96Jp8xJz8mIOmPkr3DSq0Ra840ZCyHshcAF/XVE799iKlmDkzCIgko9U0Nlq GXL3nKsUirZGBsMZ9WJPldN75VDLWC16kzzNuEYmFDhD8S8Yz8+mOce8oKssIA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266066; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DMBmqmnWEjfSXOwfzlEPnQ5lFYlfwryVt7mDU+69Iks=; b=PozyiboAHkf2qHast+04M9gDxRonfLssXEMuVyRwKBsF5e5qJtHXQxngzwgdho6JPCK7aY kG4MiN1R13+lWgBQ== From: "tip-bot2 for Chen Yu" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: sched/core] sched/cache: Fix cache aware scheduling enabling for multi LLCs system Cc: Chen Yu , Tim Chen , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: =?utf-8?q?=3C6328a8a7f40925cec2a712d81ee58128a4c4444a=2E1778703?= =?utf-8?q?694=2Egit=2Etim=2Ec=2Echen=40linux=2Eintel=2Ecom=3E?= References: =?utf-8?q?=3C6328a8a7f40925cec2a712d81ee58128a4c4444a=2E17787036?= =?utf-8?q?94=2Egit=2Etim=2Ec=2Echen=40linux=2Eintel=2Ecom=3E?= Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926606460.711.5977359466749101809.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the sched/core branch of tip: Commit-ID: 5beff4f087277901444787d4b7af6b3a93c34c54 Gitweb: https://git.kernel.org/tip/5beff4f087277901444787d4b7af6b3a9= 3c34c54 Author: Chen Yu AuthorDate: Wed, 13 May 2026 13:39:24 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 18 May 2026 21:33:18 +02:00 sched/cache: Fix cache aware scheduling enabling for multi LLCs system If there are multiple LLCs in the system, cache aware scheduling should be enabled. However, there is a corner case where, if there is a single NUMA node and a single LLC per node, cache aware scheduling will be turned on in the current implementation - because at this moment, the parent domain has not yet been degenerated, and it is possible that the current domain has the same cpu span as its parent. There is no need to turn cache aware scheduling on in this scenario. Fix it by iterating the parent domains to find a domain that is a superset of the current sd_llc, so that later, after the duplicated parent domains have been degenerated, cache aware scheduling will take effect. For example, the expected behavior would be: 2 sockets, 1 LLC per socket: MC span=3D0-3, PKG span=3D0-7, has_multi_llcs= =3Dtrue 1 socket, 2 LLCs per socket: MC span=3D0-3, PKG span=3D0-7, has_multi_llcs= =3Dtrue 2 sockets, 2 LLCs per socket: MC span=3D0-3, PKG span=3D0-7, has_multi_llcs= =3Dtrue 1 socket, 1 LLC per socket: MC span=3D0-3, PKG span=3D0-3, has_multi_llcs= =3Dfalse This bug was reported by sashiko. Fixes: d59f4fd1d303 ("sched/cache: Enable cache aware scheduling for multi = LLCs NUMA node") Signed-off-by: Chen Yu Co-developed-by: Tim Chen Signed-off-by: Tim Chen Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/6328a8a7f40925cec2a712d81ee58128a4c4444a.177= 8703694.git.tim.c.chen@linux.intel.com --- kernel/sched/topology.c | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index c257134..4b7c64c 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -1009,6 +1009,37 @@ static bool alloc_sd_llc(const struct cpumask *cpu_m= ap, #endif =20 /* + * Return true if @sd belongs to an LLC group whose enclosing + * partition spans more than one LLC. @sd must be the topmost + * SD_SHARE_LLC domain. + * + * Any duplicated parent domains with the same span as @sd are + * skipped: before cpu_attach_domain() degeneration these still + * exist, after degeneration the loop is a no-op. This makes the + * helper usable both during sched domain build and against an + * already-attached domain tree. + * + * Note: For systems with a single LLC per node, cache-aware + * scheduling is still enabled when multiple nodes exist. + * However, NUMA balancing decisions take precedence over + * cache-aware scheduling. Conversely, if there is only one + * LLC per partition, cache-aware scheduling should be disabled. + */ +static bool sd_in_multi_llcs(struct sched_domain *sd) +{ + struct sched_domain *sdp =3D sd->parent; + + /* it does not make sense to aggregate to 1 CPU */ + if (sd->span_weight =3D=3D 1) + return false; + + while (sdp && sdp->span_weight =3D=3D sd->span_weight) + sdp =3D sdp->parent; + + return !!sdp; +} + +/* * Return the canonical balance CPU for this group, this is the first CPU * of this group that's also in the balance mask. * @@ -3017,9 +3048,11 @@ build_sched_domains(const struct cpumask *cpu_map, s= truct sched_domain_attr *att * NUMA imbalance stats for the hierarchy. */ if (sd->parent) { - if (IS_ENABLED(CONFIG_NUMA)) - adjust_numa_imbalance(sd); - has_multi_llcs =3D true; + if (IS_ENABLED(CONFIG_NUMA)) + adjust_numa_imbalance(sd); + + if (sd_in_multi_llcs(sd)) + has_multi_llcs =3D true; } } }