From nobody Mon May 25 00:09:09 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E2503B0AE9; Wed, 20 May 2026 08:33:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266038; cv=none; b=qsah7EJX+Ml7BvZ9X3AWiyAWDBmr0lPTpo9TR90zal+BEIXRdZUJljCNldEJp1mooY/UhswwhNE/8+Vh/RUXRbLV7wfGJWQP/a0LgHYWuwsLvPxq+p3Ui+mF5o3qKBh8tIMXoeP66Agz4/cKZE3cxmhUyLvWU8wnmzAADcRU8IU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266038; c=relaxed/simple; bh=gGyuBd0rKfBayFAzySfHfDxxlCcaJrJjWwocwzpzBcY=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=cp7z3sj6TD/LxINBjW90gEgvxLUq2hiOawhJ2FMhF952mlTGyaUDK9R9YSWGK1qMm3PqUuGGAWq0gtRi9IJNzi+ah4Lpl3h+FNIBpoIWTkoS8xn63ucnCtEc3LcxzyZYWHozngwqWBwDx0FBILvM1oDynbMQbaauCCTEldn0qWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LN7/20fC; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4SCbZd0c; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LN7/20fC"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4SCbZd0c" Date: Wed, 20 May 2026 08:33:54 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266035; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f5ji5x77enjN8V+C8qOXNavYo+BcMFIwCf5QLxbND1A=; b=LN7/20fCg/CrgqGNxy3J0FMZGYu8363ZjlygDxV+H4KeWtUBfXSzSwgYy54nQTc0YNUiX7 Eqr1p0FgFDh86LvUgiCMO4MV3ZhJj73zfIr9RUDQiMpMyZMg4iGy6N/oogZ9x9MVjW8W3L LMwgU4mRl3TGF/m9MgOaav/AOqgdMK7SSs6vfTgK9SvTUMhTXjnYxu9QOfBBvR6GCFf98d J/beb37Wf0yA++iqzKc2fgCKvzPWCaab6KURkrUE+taJ5ou32E8L405Txf5AFs0Pfl9MJX FdJh+KRvyRHXVJH9E/fjvZUBtMej0On+K17JEdChWWg2FyVbkT+xKE2q/Jp88w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266035; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f5ji5x77enjN8V+C8qOXNavYo+BcMFIwCf5QLxbND1A=; b=4SCbZd0cCwkNIphl/pZvbmDKWbDKOh5j7hSj8kTTNh7Gudq0vZ4iwtIQBDsFfQ3gSTWxTm Q02b5myWlwLrSiBA== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints and cache_extra_regsfor ICX Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-2-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-2-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926603412.711.5703170190967246459.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: acc41cdcb091453f48381d1c0d2e76b63c9d985f Gitweb: https://git.kernel.org/tip/acc41cdcb091453f48381d1c0d2e76b63= c9d985f Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:33 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:02 +02:00 perf/x86/intel: Update event constraints and cache_extra_regsfor ICX Update perf hard-coded event constraints and cache_extra_regs[] for Icelake server according to the latest ICX perfmon events (v1.30). Since the value of cache extra registers differs with previous generations, introduce new snc_hw_cache_extra_regs[] to represent the value of extra registers on ICX. ICX perfmon events: https://github.com/intel/perfmon/blob/main/ICX/events/icelakex_core.json Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-2-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 48 +++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 2b05587..db409ca 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -310,10 +310,11 @@ static struct extra_reg intel_skl_extra_regs[] __read= _mostly =3D { static struct event_constraint intel_icl_event_constraints[] =3D { FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */ - FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ + FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ - FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ - FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ + FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ + FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */ METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), @@ -1019,6 +1020,41 @@ static __initconst const u64 skl_hw_cache_extra_regs }, }; =20 +static __initconst const u64 snc_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D +{ + [ C(LL ) ] =3D { + [ C(OP_READ) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ + [ C(RESULT_MISS) ] =3D 0x3FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ + }, + [ C(OP_WRITE) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x3F3FFC0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ + [ C(RESULT_MISS) ] =3D 0x3F3FC00002, /* OCR.DEMAND_RFO.L3_MISS */ + }, + [ C(OP_PREFETCH) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x0, + [ C(RESULT_MISS) ] =3D 0x0, + }, + }, + [ C(NODE) ] =3D { + [ C(OP_READ) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */ + [ C(RESULT_MISS) ] =3D 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM = */ + }, + [ C(OP_WRITE) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x104000002, /* OCR.DEMAND_RFO.LOCAL_DRAM */ + [ C(RESULT_MISS) ] =3D 0x730000002, /* OCR.DEMAND_RFO.REMOTE_DRAM */ + }, + [ C(OP_PREFETCH) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x0, + [ C(RESULT_MISS) ] =3D 0x0, + }, + }, +}; + #define SNB_DMND_DATA_RD (1ULL << 0) #define SNB_DMND_RFO (1ULL << 1) #define SNB_DMND_IFETCH (1ULL << 2) @@ -8154,17 +8190,19 @@ __init int intel_pmu_init(void) =20 case INTEL_ICELAKE_X: case INTEL_ICELAKE_D: + memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_ext= ra_regs)); x86_pmu.pebs_ept =3D 1; pmem =3D true; - fallthrough; + goto snc_common; case INTEL_ICELAKE_L: case INTEL_ICELAKE: case INTEL_TIGERLAKE_L: case INTEL_TIGERLAKE: case INTEL_ROCKETLAKE: + memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_ext= ra_regs)); + snc_common: x86_pmu.late_ack =3D true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event= _ids)); - memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_ext= ra_regs)); hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] =3D -1; intel_pmu_lbr_init_skl(); =20