From nobody Mon May 25 00:09:40 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80B473AFD10; Wed, 20 May 2026 08:33:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266036; cv=none; b=qRuXNqoRZrArlomR73q+if9nqasyhDfHZav3La7MHpC5ajUFkZaeNubZZdL/sEfIvjxKg49daAmHRZY3aYVT0jiuX/uZResNoDCoV4+CtTQYUApdPuhTVBP6668Ae879L/422A1ydKYQRHCCSQjLqYxsNd25iHQjo+t/zRegba8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266036; c=relaxed/simple; bh=p8EKixpfNQtEnmq+zEM+NzMERxanVUbYdHbQoUZE0VM=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Sz7xQsgJECnJ2d0Kn4ru3svf4g3GJJTEnSs6nO+mvREcyoe6fh/qHVzmTsoM3L+I9LN2yZIyxrD/VnL33MJBi/S6NF9fy2YPTn9coXU7h604Jt1OHXFpKAekAjQPkkRrENaDgup/IzEhCBsV2QUEklFy3mCePvVFKCjIx4QzGGA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=M02pXbRs; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sfgUElSJ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="M02pXbRs"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sfgUElSJ" Date: Wed, 20 May 2026 08:33:52 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266034; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ag5rXs77kYbMcVDdyL9Q+aZNaWpQW7f8AhouMb/Yup8=; b=M02pXbRsqXW8HwK1CLK+uNwABlJAFpEo1Q/UHFr+CmTNE9q/96saYyTAocxVZ99su8b7Z7 2Tdi4vMGr5rGblV/oZrCOKbxdwp2x5mrjVr9FzwLmAd9aRKjp9VvkMtWwFT61k3eotinf4 tx3gfTpJCnZGBgvws/n5mzdzlrelRni+qmkk18xHUiQQqsHOialF5ykcsvw43lngabJuKd Qp1Ch69VOwZGM1ICH1Iv8zadjxtuxvXfSIprV+vXbbcUclrhGYLbfDzmBgac4grCDe8uOP eWHlvqrSnSSeyeUnYWLjEtI0CtBqDeyaovy9M4emgKX+Ehabko/OrdJzaJUsMw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266034; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ag5rXs77kYbMcVDdyL9Q+aZNaWpQW7f8AhouMb/Yup8=; b=sfgUElSJxlaipVVSU27TTxpZgINgKLUK9WF70sdAh0lXKB8LaDHP6B/0yz60pxQdvftEgv 4kE57lJbtlvOC3AQ== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints and cache_extra_regsfor SPR Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-3-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-3-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926603265.711.1231593039500795361.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 30d82ddee085b4b0f9a1b5bded53acaca68d9a52 Gitweb: https://git.kernel.org/tip/30d82ddee085b4b0f9a1b5bded53acaca= 68d9a52 Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:34 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:02 +02:00 perf/x86/intel: Update event constraints and cache_extra_regsfor SPR Update perf hard-coded event constraints and cache_extra_regs[] for Sapphire rapids according to the latest SPR perfmon events (v1.39). Emerald Rapids (EMR) and Granite Rapids (GNR) share exactly same event constraints and extra MSR values with SPR. No extra changes are needed for EMR and GNR. Please note the change could temporarily impact other platforms which share the hard coded data structures, but it would be fixed in subsequent patches soon. SPR perfmon events: https://github.com/intel/perfmon/blob/main/SPR/events/sapphirerapids_core.j= son Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-3-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index db409ca..932f612 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -356,11 +356,12 @@ static struct extra_reg intel_glc_extra_regs[] __read= _mostly =3D { =20 static struct event_constraint intel_glc_event_constraints[] =3D { FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ - FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ + FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ - FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ + FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ - FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ + FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */ METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), @@ -380,9 +381,13 @@ static struct event_constraint intel_glc_event_constra= ints[] =3D { =20 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf), INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), + INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), + INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf), + INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf), INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1), INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1), + INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe), INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1), INTEL_EVENT_CONSTRAINT(0xce, 0x1), INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf), @@ -714,18 +719,18 @@ static __initconst const u64 glc_hw_cache_extra_regs { [ C(LL ) ] =3D { [ C(OP_READ) ] =3D { - [ C(RESULT_ACCESS) ] =3D 0x10001, - [ C(RESULT_MISS) ] =3D 0x3fbfc00001, + [ C(RESULT_ACCESS) ] =3D 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ + [ C(RESULT_MISS) ] =3D 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ }, [ C(OP_WRITE) ] =3D { - [ C(RESULT_ACCESS) ] =3D 0x3f3ffc0002, - [ C(RESULT_MISS) ] =3D 0x3f3fc00002, + [ C(RESULT_ACCESS) ] =3D 0x3f3ffc0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ + [ C(RESULT_MISS) ] =3D 0x3f3fc00002, /* OCR.DEMAND_RFO.L3_MISS */ }, }, [ C(NODE) ] =3D { [ C(OP_READ) ] =3D { - [ C(RESULT_ACCESS) ] =3D 0x10c000001, - [ C(RESULT_MISS) ] =3D 0x3fb3000001, + [ C(RESULT_ACCESS) ] =3D 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */ + [ C(RESULT_MISS) ] =3D 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM = */ }, }, };