From nobody Mon May 25 00:09:40 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33ACC3A6B85; Wed, 20 May 2026 08:33:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266035; cv=none; b=Ec8jVyxiTvw6QDF+ZpgnNBj8Fv954gLTOza4IEiU4o2wqw4X0ZgpOxRLCW5Hw4rMUnHE+vFpnu0rePnSCCaMeZgkj/2aIMOjtmM7rNYoOk2gULZC1AYIiD0UcN63xaRxsYQPgRd5acTElrgqyIQyOZm1pGgE5zC8zefNpCU7WnE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266035; c=relaxed/simple; bh=6Rm+eXL9l6jc1o/nfuuYEisIU0TlrDFWUpNNvcDzJ00=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=JoKZJkK0pvsAbAFuutAeZT1Im1eI2sUQ3ir8JpCoOAC3z5RobHMgYBJN8gQeOwMFlbFhw6YeXMPlARe3FKbh9Ry0pao+NwI8SQtH/99gkP1IwZl7O78tyzwDXfipwL4WBQoTFQev9WOP4ssm5qdDQaJ0lvMEGYmwvRovjRQalTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=O0CbtiAP; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ad+WAiK8; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="O0CbtiAP"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ad+WAiK8" Date: Wed, 20 May 2026 08:33:51 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266032; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y+haOdO5dELZXESXQf4FpR9SZUypQQ1OuTFOfaCQTho=; b=O0CbtiAPnEX9KwR/FtFGC8i3jsVRohqOkJTQ6RY+j6SD5jiIyns9iEKKsdSVq/u1C4togw i+JV53qYSpSiUVnDKeTsvgYo+p1CryEHxiPbCA/IfZ6hCbZ10G+/hG603RggQAVMRfqR5V x7m3S5PWMwectyWemYRixC4IcospwzZS43h8VLhaTAUwzsAea5V6hy6Tq703wIev3T81Ix oZpg5Qo0ezaiK8OYt/1hL89P95ya/pvCGxDE2/GooZOkVTdIMhB1SuYKBYS1HQeZOkQPZc lYpbBzh2wK6wex9vP6pisBzzHOHhswhoUxJ2duj7oGAY/WV77fM83sbdMcVGhw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266032; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y+haOdO5dELZXESXQf4FpR9SZUypQQ1OuTFOfaCQTho=; b=ad+WAiK8HdgVhl3OKP4COKu7CXFJelX+yF0Bj1afqt1PY4ES5z6o+mnM6jblRdTCHm7RLr QDhHYF242dMNi3DA== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints for DMR Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-4-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-4-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926603115.711.6385845939244908826.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 070bd45e1dba684bfa4e7fdaa8ef8efa99b4572e Gitweb: https://git.kernel.org/tip/070bd45e1dba684bfa4e7fdaa8ef8efa9= 9b4572e Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:35 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:03 +02:00 perf/x86/intel: Update event constraints for DMR Add missed event constraint for 0x0200 event and add comments to show the event names in pnc_hw_cache_extra_regs[]. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-4-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 932f612..da2ade0 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -466,11 +466,12 @@ static struct extra_reg intel_lnc_extra_regs[] __read= _mostly =3D { =20 static struct event_constraint intel_pnc_event_constraints[] =3D { FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ - FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */ + FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ - FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ + FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD= */ + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ - FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */ + FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */ METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0), METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1), METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2), @@ -821,12 +822,12 @@ static __initconst const u64 pnc_hw_cache_extra_regs { [ C(LL ) ] =3D { [ C(OP_READ) ] =3D { - [ C(RESULT_ACCESS) ] =3D 0x4000000000000001, - [ C(RESULT_MISS) ] =3D 0xFFFFF000000001, + [ C(RESULT_ACCESS) ] =3D 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_R= ESPONSE */ + [ C(RESULT_MISS) ] =3D 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS= */ }, [ C(OP_WRITE) ] =3D { - [ C(RESULT_ACCESS) ] =3D 0x4000000000000002, - [ C(RESULT_MISS) ] =3D 0xFFFFF000000002, + [ C(RESULT_ACCESS) ] =3D 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESP= ONSE */ + [ C(RESULT_MISS) ] =3D 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */ }, }, };