From nobody Mon May 25 00:08:59 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 366AA3B4E94; Wed, 20 May 2026 08:33:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266032; cv=none; b=ls0ARZFB9MnYTHl65uJ7bM+7JQXx3QIEP927LOYr3XzZqFHsgMwtUCy1yuFYRYz+aoB38lrlbL5OkakhW1q76CpyxS5iWyD6wBdgi5bZMgcDW12WFIHN5DDHJMv0/N5MQXyNyilm1wwQZPo4Y7tDMr8yP/6eEE/q+7dDp3CZT1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266032; c=relaxed/simple; bh=3BZDWGcpEZkJFpF4aOF4Qi/AkcdgvEHXRqEbjCrx/Q4=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=TGM457GUqlyIxpxbHn+FOqQ5Dg0E0FfERT/OsmBNFfgHWEKfKsZMarGRMXFRpo/LVCnhAIj8WlJBT4Sxw5/lGv2xFo6uhpR4R+FxHbfCccEe6xYt2NciNZTL+iMymHxm18Xs1B+XW1S0zyMvU/m4uzd1jv+udNjLD7rLwOJX+xI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QkFAhuan; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kK+DR27O; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QkFAhuan"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kK+DR27O" Date: Wed, 20 May 2026 08:33:48 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266029; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iTzP2drqZF+dWFtp1ANjkhbwPaJGRdm6RFNcsYTuz+4=; b=QkFAhuanW94dBPxngXnHhWQkYa9SeJnjv0u/VFCOXCxR/bKSY5Te04B3zFfAwtOMAHhDw0 Nzf9FU+J31lCExgqed4GQfpYTXruI9lCwF4l5tM8b5TkqWUvt8mo7rs6RNXZ3vAYEco2r4 UUhXDeQ/k2dPaG4Rw8ZrCMCudwlvI8k9J5E1tAetYLItgV8gFyzq9ylidKvM1zkdydaP9F gp6UZ/gp9jDjweZVhoE6tfpMqRY2+6Qb9cFn6lYvKQzY20SAo/oSlo66d9bX4eiH9pHi2z 1IBxpoXbR2sZdFG9vGwohgv3C98rCZBi+AqToIajDwuUNar6oXw3Ge5T8hpDHQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266029; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iTzP2drqZF+dWFtp1ANjkhbwPaJGRdm6RFNcsYTuz+4=; b=kK+DR27OmxbDWQfTuF4ikR3ubvHTOFVM9AgdNZHt6JU+nL1T4/euAxUJRDUbqYziLnRaq0 AL5eEb7jItL4YgDA== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints and cache_extra_regsfor MTL Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-6-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-6-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926602844.711.8964283966970684448.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: e99fb45436eaa4ac1b72a8e4af56381f59759b0c Gitweb: https://git.kernel.org/tip/e99fb45436eaa4ac1b72a8e4af56381f5= 9759b0c Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:37 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:03 +02:00 perf/x86/intel: Update event constraints and cache_extra_regsfor MTL Update perf hard-coded event constraints and cache_extra_regs[] for Meteor Lake according to the latest MTL perfmon events (V1.21). MTL P-core (redwoodcove) inherits same perf events list from previous generation (Goldencove), but the E-core (Crestmont) brings some difference on the perf event list comparing with Gracemont. So apply the changes for Crestmont core. MTL perfmon events: https://github.com/intel/perfmon/blob/main/MTL/events/meteorlake_redwoodcov= e_core.json https://github.com/intel/perfmon/blob/main/MTL/events/meteorlake_crestmont_= core.json Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-6-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 27 +++++++++++++++++++++++++-- arch/x86/events/intel/ds.c | 7 +++++++ arch/x86/events/perf_event.h | 2 ++ 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index be86051..8161912 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2494,6 +2494,21 @@ static __initconst const u64 grt_hw_cache_extra_regs }, }; =20 +static __initconst const u64 cmt_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { + [C(LL)] =3D { + [C(OP_READ)] =3D { + [C(RESULT_ACCESS)] =3D 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ + [C(RESULT_MISS)] =3D 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ + }, + [C(OP_WRITE)] =3D { + [C(RESULT_ACCESS)] =3D 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ + [C(RESULT_MISS)] =3D 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */ + }, + }, +}; =20 static __initconst const u64 arw_hw_cache_extra_regs [PERF_COUNT_HW_CACHE_MAX] @@ -7677,6 +7692,15 @@ static __always_inline void intel_pmu_init_grt(struc= t pmu *pmu) intel_pmu_ref_cycles_ext(); } =20 +static __always_inline void intel_pmu_init_cmt(struct pmu *pmu) +{ + intel_pmu_init_grt(pmu); + memcpy(hybrid_var(pmu, hw_cache_extra_regs), + cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); + hybrid(pmu, pebs_constraints) =3D intel_cmt_pebs_event_constraints; + hybrid(pmu, extra_regs) =3D intel_cmt_extra_regs; +} + static __always_inline void intel_pmu_init_lnc(struct pmu *pmu) { intel_pmu_init_glc(pmu); @@ -8489,8 +8513,7 @@ __init int intel_pmu_init(void) =20 /* Initialize Atom core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; - intel_pmu_init_grt(&pmu->pmu); - pmu->extra_regs =3D intel_cmt_extra_regs; + intel_pmu_init_cmt(&pmu->pmu); =20 intel_pmu_pebs_data_source_mtl(); pr_cont("Meteorlake Hybrid events, "); diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index efab3cb..75b7f6f 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1296,6 +1296,13 @@ struct event_constraint intel_grt_pebs_event_constra= ints[] =3D { EVENT_CONSTRAINT_END }; =20 +struct event_constraint intel_cmt_pebs_event_constraints[] =3D { + /* Allow all events as PEBS with no flags */ + INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), + INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff), + EVENT_CONSTRAINT_END +}; + struct event_constraint intel_arw_pebs_event_constraints[] =3D { /* Allow all events as PEBS with no flags */ INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff), diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 40d6fe0..a9acfbe 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1710,6 +1710,8 @@ extern struct event_constraint intel_glp_pebs_event_c= onstraints[]; =20 extern struct event_constraint intel_grt_pebs_event_constraints[]; =20 +extern struct event_constraint intel_cmt_pebs_event_constraints[]; + extern struct event_constraint intel_arw_pebs_event_constraints[]; =20 extern struct event_constraint intel_nehalem_pebs_event_constraints[];