From nobody Mon May 25 00:09:08 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 778EA3B19C6; Wed, 20 May 2026 08:33:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266029; cv=none; b=sXkm7XrkBVLdTIogle4n3yS2SD54XGsTRRzGSxaXA5S9T3Sm9nWcsSc4td1atlp3tm+r6NQhua/Md42CZTcVmbhebRDtb5bzfiu78WNxBkaCGFoq4laiS0we9mo6oV0P5RlmYBVGl3wcRn8OGvmH9oEGGG3E3C4YOS5pggpjOBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266029; c=relaxed/simple; bh=whNPrNEM12eePE/T4Vo4iZG4jte1uv4ashYziS2llqg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=kFsMwbr0i4brEZ5a5hKheUUvY428IPGhm5w4DWQSZCSpySVymHgrrkwG1JT/D03O5xPNnTloGzH58aso8hLccpXdCeri7MTltGVLOWBdHoJ7Y2FZGrQfJFaT5ApujptxBy3vJvDYXMjer41EdPQj/dhEhTiiBg6yczL3zljBmhA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lXL9/xN1; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XcWqBm+/; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lXL9/xN1"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XcWqBm+/" Date: Wed, 20 May 2026 08:33:45 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266027; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fyu7290h9rjdvW1lly4Vl4ktLXgrhr44SzTrJ2y9SC4=; b=lXL9/xN1qs/LKHxT8AbMbQeKV6f7ukogf4QZfuDpv7SusNrJQEf8uhoeB0OCERHAQXI3Lq ko4NMxqKE7bIFotKxQfz4LFOyKhc8Nl7WLaqvqeCAEnlSoUH4eopDSptPCTn6l0aP0j6KA SNFz0ly/DtwdItjZh4q1qpdimfV3nI7uqdUYdRh1GB6SRIGKjFPiwNYYTmDJP3TuAJ0vH2 OsMQHjvk++zkPq9QSe6bZhMtjzZ/kNy3zQlN24cZXuGIvCw5emvLLDk92uYf9jlXNMyQ86 o0B/5rQ3JnCheb5XYunu6OzRYk7RzjrsL0uW9OlMyxtVlr00YC/7YPixN0X96Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266027; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fyu7290h9rjdvW1lly4Vl4ktLXgrhr44SzTrJ2y9SC4=; b=XcWqBm+/6Ebv+RvJujWTYUqbpIujXVSn2LHYeMl4kgqYd7qbEFTTBrPo1NPY96Gj2R2ERm LHA3v6BYHmVI/PAg== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints and cache_extra_regsfor ARL Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-8-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-8-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926602569.711.3588621043059398652.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 0073ed169226f4ed65e339f770118f54ce4e1370 Gitweb: https://git.kernel.org/tip/0073ed169226f4ed65e339f770118f54c= e4e1370 Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:39 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:04 +02:00 perf/x86/intel: Update event constraints and cache_extra_regsfor ARL Update perf hard-coded event constraints and cache_extra_regs[] for Arrowlake according to the latest ARL perfmon events (V1.17). ARL shares almost same event constraints and extra MSR configuration with LNL except 2 differences. - ARL P-core has different extra MSR value for OCR.DEMAND_DATA_RD.L3_MISS and OCR.DEMAND_RFO.L3_MISS. So introduce arl_lnc_hw_cache_extra_regs[] to reflect the difference. - ARL-H has extra LPE cores which use crestmont architectures. Add crestmont specific event constraints and hw_cache_extra_regs[] for LPE cores. ARL perfmon events: https://github.com/intel/perfmon/blob/main/ARL/events/arrowlake_lioncove_co= re.json https://github.com/intel/perfmon/blob/main/ARL/events/arrowlake_skymont_cor= e.json https://github.com/intel/perfmon/blob/main/ARL/events/arrowlake_crestmont_c= ore.json Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-8-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 56 ++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index dc0991c..86ed34d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -850,6 +850,24 @@ static __initconst const u64 lnc_hw_cache_extra_regs }, }; =20 +/* ARL specific lioncove hw_cache_extra_regs[] variant. */ +static __initconst const u64 arl_lnc_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D +{ + [ C(LL ) ] =3D { + [ C(OP_READ) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ + [ C(RESULT_MISS) ] =3D 0xFE7F8000001, /* OCR.DEMAND_DATA_RD.L3_MISS */ + }, + [ C(OP_WRITE) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ + [ C(RESULT_MISS) ] =3D 0xFE7F8000002, /* OCR.DEMAND_RFO.L3_MISS */ + }, + }, +}; + static __initconst const u64 pnc_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] @@ -8564,16 +8582,41 @@ __init int intel_pmu_init(void) case INTEL_WILDCATLAKE_L: pr_cont("Pantherlake Hybrid events, "); name =3D "pantherlake_hybrid"; + + intel_pmu_init_hybrid(hybrid_big_small); + + /* Initialize big core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; + intel_pmu_init_lnc(&pmu->pmu); + goto lnl_common; =20 - case INTEL_LUNARLAKE_M: case INTEL_ARROWLAKE: + pr_cont("Arrowlake Hybrid events, "); + name =3D "arrowlake_hybrid"; + + intel_pmu_init_hybrid(hybrid_big_small); + + /* Initialize big core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; + intel_pmu_init_lnc(&pmu->pmu); + memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs), + arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); + + goto lnl_common; + + case INTEL_LUNARLAKE_M: pr_cont("Lunarlake Hybrid events, "); name =3D "lunarlake_hybrid"; =20 - lnl_common: intel_pmu_init_hybrid(hybrid_big_small); =20 + /* Initialize big core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; + intel_pmu_init_lnc(&pmu->pmu); + + lnl_common: + x86_pmu.pebs_latency_data =3D lnl_latency_data; x86_pmu.get_event_constraints =3D mtl_get_event_constraints; x86_pmu.hw_config =3D adl_hw_config; @@ -8584,10 +8627,6 @@ __init int intel_pmu_init(void) extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; =20 - /* Initialize big core specific PerfMon capabilities.*/ - pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; - intel_pmu_init_lnc(&pmu->pmu); - /* Initialize Atom core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; intel_pmu_init_skt(&pmu->pmu); @@ -8611,6 +8650,8 @@ __init int intel_pmu_init(void) /* Initialize big core specific PerfMon capabilities. */ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; intel_pmu_init_lnc(&pmu->pmu); + memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs), + arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); =20 /* Initialize Atom core specific PerfMon capabilities. */ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; @@ -8618,8 +8659,7 @@ __init int intel_pmu_init(void) =20 /* Initialize Lower Power Atom specific PerfMon capabilities. */ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX]; - intel_pmu_init_grt(&pmu->pmu); - pmu->extra_regs =3D intel_cmt_extra_regs; + intel_pmu_init_cmt(&pmu->pmu); =20 intel_pmu_pebs_data_source_arl_h(); pr_cont("ArrowLake-H Hybrid events, ");