From nobody Mon May 25 00:09:51 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A5603AFD17; Wed, 20 May 2026 08:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266028; cv=none; b=EDSCTkTYb5OF7caDvXhekNkUxFwfrQYi+cY1IiXmkfDHOTYMIdwwGrp+z0otCyGE7eEjJmXUIPgUNxUb9XcvnHYqYPsLA/T/a3Phn4Atql76+qHdMl5C3wh72QbNVRUe5zqplM16xlaaE4+i9RmYoSk6TW4SNlh5hGxUEwyCTh0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266028; c=relaxed/simple; bh=59FrdxHF8ZuR2NBy0970TKzev16QTkIHV2acMJ9Bg14=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=b4cR9r2kUxjeQBNiK97vSdZ63YQ+hZ8IHivRLOTupfqfK8IJrVu/Kft7ZPSNiKsHtuz5Yb/t2hWpztbZo1jvnYtpYE+iqqeE4wEc4jLzJ1wiqZE1ZLNnpbeqFIJsasUVZn+p2JQIlm/vpkQOoLTq5SygpJEAtGnZGHv5cGuXC/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dOyABYfj; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MvTgxWsl; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dOyABYfj"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MvTgxWsl" Date: Wed, 20 May 2026 08:33:44 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266025; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KzoYUyi7atvDN2yzeiL4DLSERdhfVCfInZ/Hc+2FLVY=; b=dOyABYfjcl24OmpItmjyG4DhlQw1MvBZ3bK0cXs65E+zd68tgc0EvOc/PNchRJJ126rmgA Ip839BDVOutx/gWM+oR5DTPy0OS5Pm4F36NCmgmmGaCj1lfEhRbbqNUgDkdGBpBX3T13kr UkfAMDuh7Kw0nXH+Ya+ljA9uk2SVIFDFidCyObs/FJ3F9UYl5XdyRqV7sPEZ5nAAeEMqKe RMEb6CgikzjGBD4CAfkznNN6AweIghHH//4qIv1dc57lECYIithmKA76ps0+QxToE1e54e XVazvOqx+xxL1Cp3Qjm6gllNTBgGUkMJPUbByfwd/M0XNsk792tQV5SlAj4oWw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266025; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KzoYUyi7atvDN2yzeiL4DLSERdhfVCfInZ/Hc+2FLVY=; b=MvTgxWslY1lLHjYSC/n92nutFoJtJBoyD2m/GCrkigN+iKWMLH7RjuHldOs//Ztc665FOh Gn2bOBaPKAwmUEBw== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints for PTL Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-9-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-9-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926602431.711.11064062842167769951.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 65fd435095bb299b9c50d3285d4e6569b79b86e2 Gitweb: https://git.kernel.org/tip/65fd435095bb299b9c50d3285d4e6569b= 79b86e2 Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:40 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:04 +02:00 perf/x86/intel: Update event constraints for PTL Update perf hard-coded event constraints for Pantherlake according to the latest PTL perfmon events (V1.05). PTL has almost same perf event list as LNL except some PEBS event constraints of E-core (exactly same on P-core). Define intel_dkt_pebs_event_constraints[] to reflect the PTL E-core specific PEBS event constraints. PTL perfmon events: https://github.com/intel/perfmon/blob/main/PTL/events/pantherlake_cougarcov= e_core.json https://github.com/intel/perfmon/blob/main/PTL/events/pantherlake_darkmont_= core.json Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-9-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 20 ++++++++++++++++---- arch/x86/events/intel/ds.c | 7 +++++++ arch/x86/events/perf_event.h | 2 ++ 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 86ed34d..60a107c 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7790,6 +7790,13 @@ static __always_inline void intel_pmu_init_skt(struc= t pmu *pmu) static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); } =20 +/* Hybrid client variant. */ +static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu) +{ + intel_pmu_init_skt(pmu); + hybrid(pmu, pebs_constraints) =3D intel_dkt_pebs_event_constraints; +} + static __always_inline void intel_pmu_init_arw(struct pmu *pmu) { intel_pmu_init_grt(pmu); @@ -8588,6 +8595,9 @@ __init int intel_pmu_init(void) /* Initialize big core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; intel_pmu_init_lnc(&pmu->pmu); + /* Initialize Atom core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; + intel_pmu_init_dkt_hybrid(&pmu->pmu); =20 goto lnl_common; =20 @@ -8602,6 +8612,9 @@ __init int intel_pmu_init(void) intel_pmu_init_lnc(&pmu->pmu); memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs), arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); + /* Initialize Atom core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; + intel_pmu_init_skt(&pmu->pmu); =20 goto lnl_common; =20 @@ -8614,6 +8627,9 @@ __init int intel_pmu_init(void) /* Initialize big core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; intel_pmu_init_lnc(&pmu->pmu); + /* Initialize Atom core specific PerfMon capabilities.*/ + pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; + intel_pmu_init_skt(&pmu->pmu); =20 lnl_common: =20 @@ -8627,10 +8643,6 @@ __init int intel_pmu_init(void) extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; =20 - /* Initialize Atom core specific PerfMon capabilities.*/ - pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; - intel_pmu_init_skt(&pmu->pmu); - intel_pmu_pebs_data_source_lnl(); break; =20 diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index ce23b50..5159ada 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1303,6 +1303,13 @@ struct event_constraint intel_cmt_pebs_event_constra= ints[] =3D { EVENT_CONSTRAINT_END }; =20 +struct event_constraint intel_dkt_pebs_event_constraints[] =3D { + /* Allow all events as PEBS with no flags */ + INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff), + INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff), + EVENT_CONSTRAINT_END +}; + struct event_constraint intel_arw_pebs_event_constraints[] =3D { /* Allow all events as PEBS with no flags */ INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff), diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index a9acfbe..982864c 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1712,6 +1712,8 @@ extern struct event_constraint intel_grt_pebs_event_c= onstraints[]; =20 extern struct event_constraint intel_cmt_pebs_event_constraints[]; =20 +extern struct event_constraint intel_dkt_pebs_event_constraints[]; + extern struct event_constraint intel_arw_pebs_event_constraints[]; =20 extern struct event_constraint intel_nehalem_pebs_event_constraints[];