From nobody Mon May 25 00:09:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFE093AEF2D; Wed, 20 May 2026 08:33:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266027; cv=none; b=Jpa9YZAEdiqv5BM9gC48Bv6ZWs+bQ1cqPoM0AJbh5hSpNbVBdUxm+Wrv0ayXw7utR0RlRn3oJv/f44PDsdIvP4E+zwdZAPoFggvRQuK8cb8jQQ3F+4gLLIH4LkIevRHGYRgZB38bbCOChqf/MLCOS/AgYIslfYAjPOR1/OkR9GI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266027; c=relaxed/simple; bh=yj3UwGj7GsZuVzmBkQm4IvZ+MBacGvBN7E85QQ3cPL0=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=RhpvDIKGISQYZxYg2ku0J59S0XuyLP11IAHbzNnbIMVBX+inqSoWseKRYErrpLIgKezKIbO/Q+uwXTSJBunlPTcfVGBEjog1l01pKu4Om/IAoHP+hBuHmtiypZVhIKiqma8L4psBQO0vyygooDsbznRr+MKezEzHy2Z+Th3TPV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MLvlqkWN; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=X/hzdaLb; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MLvlqkWN"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="X/hzdaLb" Date: Wed, 20 May 2026 08:33:42 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266024; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OHOAkv00Zc4rixx6lwqaSgugGhtWbQEeXn1idgahHIU=; b=MLvlqkWNuk1OAD+Ntk6BGTbOA5MvtDMK0aSsJwWfDK6YH2ljcPQKjdibuKY7TDnbta2SJJ QY3ePGIVE9aRYqCpUN8crytTDwSn3xmNLHUEYT7whHZSdcjdvmE1m7MkNcNNAwThe4aWhr 8YywSDk2aurOEDT5DVh+424rpBJ0N9wUX5d3TAmHKjQTHCglOe02T1Cz9gl81DEiPs7sVA 9S96mtYJkmv68U2U+udF9r/Vx4XMy4Gcy4ULnzFLYZ/Z1zy7YJQRlumSXagp6xd2SFtf/M ZIR0tISVFEo/oyCtEUPGjSHLj6Z5nbGT0KezpKhGe1k2swTFCpZVwe7Dg/a/pg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266024; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OHOAkv00Zc4rixx6lwqaSgugGhtWbQEeXn1idgahHIU=; b=X/hzdaLbit91Uy0Ef980pQDZXhEELvSLeA6UYedGVce8Uslxdm/lIXHxa32ku5fcdL1j9x 1gDcRKTsHmwjE3AQ== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints and cache_extra_regsfor NVL Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-10-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-10-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926602289.711.9637936713745397653.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 42f47511d9795dd4ddeca7145e171f75a1a7b8eb Gitweb: https://git.kernel.org/tip/42f47511d9795dd4ddeca7145e171f75a= 1a7b8eb Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:41 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:04 +02:00 perf/x86/intel: Update event constraints and cache_extra_regsfor NVL Update perf hard-coded event constraints and cache_extra_regs[] for Novalake according to the latest NVL perfmon events. The 4 PRECISE_OMR events (0xd4) are broken on Arcticwolf and would be removed from upcoming released event list, so delete them from event constraints and extra_regs array accordingly. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-10-dapeng1.mi@linux.in= tel.com --- arch/x86/events/intel/core.c | 55 ++++++++++++++++++++++------------- arch/x86/events/intel/ds.c | 11 +------- arch/x86/events/perf_event.h | 2 +- 3 files changed, 36 insertions(+), 32 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 60a107c..332761d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -241,20 +241,21 @@ static struct event_constraint intel_skt_event_constr= aints[] __read_mostly =3D { =20 static struct event_constraint intel_arw_event_constraints[] __read_mostly= =3D { FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ + FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */ FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ - FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */ + FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */ + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */ FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */ FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */ + FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL = */ FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */ + FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */ FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */ + FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */ INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1), INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2), INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4), INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8), - INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1), - INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2), - INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4), - INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8), INTEL_UEVENT_CONSTRAINT(0x0175, 0x1), INTEL_UEVENT_CONSTRAINT(0x0275, 0x2), INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1), @@ -964,6 +965,23 @@ static __initconst const u64 pnc_hw_cache_extra_regs }, }; =20 +static __initconst const u64 cyc_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D +{ + [ C(LL ) ] =3D { + [ C(OP_READ) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_R= ESPONSE */ + [ C(RESULT_MISS) ] =3D 0xFF03F000000001, /* OMR.DEMAND_DATA_RD.L3_MISS= */ + }, + [ C(OP_WRITE) ] =3D { + [ C(RESULT_ACCESS) ] =3D 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESP= ONSE */ + [ C(RESULT_MISS) ] =3D 0xFF03F000000002, /* OMR.DEMAND_RFO.L3_MISS */ + }, + }, +}; + /* * Notes on the events: * - data reads do not include code reads (comparable to earlier tables) @@ -2570,16 +2588,12 @@ static __initconst const u64 arw_hw_cache_extra_regs [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { [C(LL)] =3D { [C(OP_READ)] =3D { - [C(RESULT_ACCESS)] =3D 0x4000000000000001, - [C(RESULT_MISS)] =3D 0xFFFFF000000001, + [C(RESULT_ACCESS)] =3D 0x4000000000000009, /* OMR.DEMAND_DATA_RD.ANY_RE= SPONSE */ + [C(RESULT_MISS)] =3D 0xFF03F000000009, /* OMR.DEMAND_DATA_RD.L3_MISS */ }, [C(OP_WRITE)] =3D { - [C(RESULT_ACCESS)] =3D 0x4000000000000002, - [C(RESULT_MISS)] =3D 0xFFFFF000000002, - }, - [C(OP_PREFETCH)] =3D { - [C(RESULT_ACCESS)] =3D 0x0, - [C(RESULT_MISS)] =3D 0x0, + [C(RESULT_ACCESS)] =3D 0x400000000000000A, /* OMR.DEMAND_RFO.ANY_RESPON= SE */ + [C(RESULT_MISS)] =3D 0xFF03F00000000A, /* OMR.DEMAND_RFO.L3_MISS */ }, }, }; @@ -2651,10 +2665,6 @@ static struct extra_reg intel_arw_extra_regs[] __rea= d_mostly =3D { INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1), INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2), INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3), - INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0), - INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1), - INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2), - INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3), INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0), INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SN= OOP_0), INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SN= OOP_1), @@ -7781,6 +7791,13 @@ static __always_inline void intel_pmu_init_pnc(struc= t pmu *pmu) static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); } =20 +static __always_inline void intel_pmu_init_cyc(struct pmu *pmu) +{ + intel_pmu_init_pnc(pmu); + memcpy(hybrid_var(pmu, hw_cache_extra_regs), + cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); +} + static __always_inline void intel_pmu_init_skt(struct pmu *pmu) { intel_pmu_init_cmt(pmu); @@ -7805,7 +7822,7 @@ static __always_inline void intel_pmu_init_arw(struct= pmu *pmu) memcpy(hybrid_var(pmu, hw_cache_extra_regs), arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); hybrid(pmu, event_constraints) =3D intel_arw_event_constraints; - hybrid(pmu, pebs_constraints) =3D intel_arw_pebs_event_constraints; + hybrid(pmu, pebs_constraints) =3D intel_dkt_pebs_event_constraints; hybrid(pmu, extra_regs) =3D intel_arw_extra_regs; static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); } @@ -8696,7 +8713,7 @@ __init int intel_pmu_init(void) =20 /* Initialize big core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; - intel_pmu_init_pnc(&pmu->pmu); + intel_pmu_init_cyc(&pmu->pmu); =20 /* Initialize Atom core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 5159ada..cb72af9 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1310,17 +1310,6 @@ struct event_constraint intel_dkt_pebs_event_constra= ints[] =3D { EVENT_CONSTRAINT_END }; =20 -struct event_constraint intel_arw_pebs_event_constraints[] =3D { - /* Allow all events as PEBS with no flags */ - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff), - INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff), - INTEL_FLAGS_UEVENT_CONSTRAINT(0x01d4, 0x1), - INTEL_FLAGS_UEVENT_CONSTRAINT(0x02d4, 0x2), - INTEL_FLAGS_UEVENT_CONSTRAINT(0x04d4, 0x4), - INTEL_FLAGS_UEVENT_CONSTRAINT(0x08d4, 0x8), - EVENT_CONSTRAINT_END -}; - struct event_constraint intel_nehalem_pebs_event_constraints[] =3D { INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 982864c..eae24bb 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1714,8 +1714,6 @@ extern struct event_constraint intel_cmt_pebs_event_c= onstraints[]; =20 extern struct event_constraint intel_dkt_pebs_event_constraints[]; =20 -extern struct event_constraint intel_arw_pebs_event_constraints[]; - extern struct event_constraint intel_nehalem_pebs_event_constraints[]; =20 extern struct event_constraint intel_westmere_pebs_event_constraints[];