From nobody Mon May 25 00:08:42 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7738630100E; Wed, 20 May 2026 08:33:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266024; cv=none; b=KxORvcax9XpZxo0fVemEws2GSz+r4TTKFRwwCQjSafDy7VN6BBN7UX9PYVBjzeNMnc6PxONJdvaSWnJr4hiF7im/tuhewVyBF7a5VszM1+8gqyq0obLFZDuye51SZFWupz+ISFn5Y6sYFG+85q6lvB5Z5byMHDlv1vkNyzILiVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779266024; c=relaxed/simple; bh=aibXjdgB8pnUzL52n2gyQEtJqClnHJR+Q5W6w7KH5VU=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=nuB+nEM6Mf1W2Qt3Vyb5sPQVcRJP86RZ7Dd+Qq6TctA8WZHZlD4HTYMDqOKN6884XRgisg0Qwr935bBwMgBvKQQvtW7G/RmGMY/f1i9YYM6A95EL+6wmOkSkGeYpSO3Ui4nKQHJ/Jn74kify1Z7eI4ztXRPWJSPpmlkuxH66UQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=AUv95OBV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9Uzgc1lK; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="AUv95OBV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9Uzgc1lK" Date: Wed, 20 May 2026 08:33:39 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1779266021; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sY+4riepV+z4niaXDdbECImDwxKf8TZxuxta68Eqpz4=; b=AUv95OBVMTKfTF7rbpybQZSlG3kB1PFmRXSl1Oyfj21bQslS9zuyH45O+27IvP2gwJa6FA dLuJA9cvRKRviDhYt0UuNbrjaoCxTeqjcDAv0IY48hdXCpr/zzBi+aNSmFJxylKe17Am0/ 46kcap1JnGi52aD6dbyH8mLFxZ3t9AfJgVN1eIvUr+LjpSljQ2GtMtGDAgSIMS2ZpV858u f30UiX3jc25aBmvJueCvWXRU9uszNLM9m35ayh1xy023habmfhoUgjdE1nvlYF5nysAJN2 8zHq5blUO5UqyqvaxxGzoniLMvJUBarK/RuMvZvjj2oUoJooE5bVvHOtg/AywQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1779266021; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sY+4riepV+z4niaXDdbECImDwxKf8TZxuxta68Eqpz4=; b=9Uzgc1lKW82hn4zL6izHIHzOZrwumh/BhSwBpySudghwgVClJ4l/dhenP0XGYem3B1Asgm +7IQD5hgzl5xwvCA== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Update event constraints and cache_extra_regsfor CWF Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515061143.338553-12-dapeng1.mi@linux.intel.com> References: <20260515061143.338553-12-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177926601987.711.16592004196528794822.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 66cc29745f2f5815482587bb9fbc1e8a3e6fcf00 Gitweb: https://git.kernel.org/tip/66cc29745f2f5815482587bb9fbc1e8a3= e6fcf00 Author: Dapeng Mi AuthorDate: Fri, 15 May 2026 14:11:43 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 19 May 2026 13:49:05 +02:00 perf/x86/intel: Update event constraints and cache_extra_regsfor CWF Update perf hard-coded event constraints and cache_extra_regs[] for Clearwater Forest according to the latest CWF perfmon events (V1.02). An important difference is that CWF introduce new extra register values for the L3 cache OCR events, so define darkmont specific dkt_hw_cache_extra_regs[] array. CWF perfmon events: https://github.com/intel/perfmon/blob/main/CWF/events/clearwaterforest_core= .json Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260515061143.338553-12-dapeng1.mi@linux.in= tel.com --- arch/x86/events/intel/core.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c4efb87..0217e70 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2582,6 +2582,22 @@ static __initconst const u64 skt_hw_cache_extra_regs }, }; =20 +static __initconst const u64 dkt_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { + [C(LL)] =3D { + [C(OP_READ)] =3D { + [C(RESULT_ACCESS)] =3D 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */ + [C(RESULT_MISS)] =3D 0x33FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */ + }, + [C(OP_WRITE)] =3D { + [C(RESULT_ACCESS)] =3D 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */ + [C(RESULT_MISS)] =3D 0x33FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */ + }, + }, +}; + static __initconst const u64 arw_hw_cache_extra_regs [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] @@ -7814,6 +7830,18 @@ static __always_inline void intel_pmu_init_dkt_hybri= d(struct pmu *pmu) hybrid(pmu, pebs_constraints) =3D intel_dkt_pebs_event_constraints; } =20 +/* + * Darkmont is used by the CWF and PTL E-cores, but their L3 OCR + * events require different extra MSR values. Keep a separate init + * function for the non-hybrid server variant. + */ +static __always_inline void intel_pmu_init_dkt(struct pmu *pmu) +{ + intel_pmu_init_dkt_hybrid(pmu); + memcpy(hybrid_var(pmu, hw_cache_extra_regs), + dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); +} + static __always_inline void intel_pmu_init_arw(struct pmu *pmu) { intel_pmu_init_grt(pmu); @@ -8148,7 +8176,7 @@ __init int intel_pmu_init(void) break; =20 case INTEL_ATOM_DARKMONT_X: - intel_pmu_init_skt(NULL); + intel_pmu_init_dkt(NULL); intel_pmu_pebs_data_source_cmt(); x86_pmu.pebs_latency_data =3D cmt_latency_data; x86_pmu.get_event_constraints =3D cmt_get_event_constraints;