From nobody Sat Jun 13 02:07:32 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42AA936B046; Mon, 11 May 2026 13:32:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778506359; cv=none; b=ebnSMPZbvw9MvMdy03kRArigyQ7VkB9lLljwBdTwi0ep/759xTgdmrEfhD2bKndCUjQvAnb5EAef9XW5+FznDxtLIMyxgT9/IWi8VmUE8ZP7VS/XO04KnJx8NAz14Lup+up7soGAujP/JlMlMHNq/6/ThZuo915sQ1PZa2e5Cpg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778506359; c=relaxed/simple; bh=kWX6EV7zjgb4KGbMIvof4KVER3bh2AHr1GeVAV2fsuU=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=lI2x+KSVr6BUqFxtNA7ndc+fp+pfkYZYWy8QTrr6fvnmJ7PDipG8ypIOP3i9LUSOMa/U4HbhVoFnNv0m2YOb7RyIT8Wx0JuB6n3nwtCeFdXL+qcO/5mURxAyR2EOJ1S4PZHiof8cN3X2b0Qm8SW7u4sANqJsOBOywMvJTZBkDmo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JN5n3kh5; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Di7anSHU; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JN5n3kh5"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Di7anSHU" Date: Mon, 11 May 2026 13:32:35 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1778506356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aB8YZ/cff3qnTgTEjGDT0GBZmOyejABp73xiYc75eEs=; b=JN5n3kh5C/JxbYn99yk58Fvvy/2Yu08wTc2tJCn/drMB21LKZZvrn+IRs7QWYCzQ8881iy Ba5w2W+yR7/0lV4ZV6h2M73l//b14O6XbhFDlmB+CuCi03rMQz9L1U9ZOhK1nUchu7QIEs InIFPtFxy6lJ0Usz6zrGv4pTjRdJ3svb6F8y3UtUuXgrPN1jYFBoGTT1cjmx2EnUNvgpDz 6mlSkrRBzy5fbDSO63OnzxdVcl13ialONt8rSPB9V7bwVVHbSSe4wDAkO86WTV2N/XTxFX JVUNMi4Pm6/lLgcIhMgUM/6pSXKGtIuBqJkN1m3/ozDLvlobfW4Oi0TeIb9YrA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1778506356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aB8YZ/cff3qnTgTEjGDT0GBZmOyejABp73xiYc75eEs=; b=Di7anSHUNuxFINGBxKh7SFW1SPVQiOzvbBJnMrwc/XO/k2Q/Bar9BcuqYskmklvLy2H2zA h06BotQ097Jkf6Dg== From: "tip-bot2 for Caleb James DeLisle" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping Cc: Caleb James DeLisle , Thomas Gleixner , "Rob Herring (Arm)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260430164157.6026-2-cjd@cjdns.fr> References: <20260430164157.6026-2-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177850635538.188840.1884235076063760047.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 02bea6ff684b62c14d5c6eafaee752d24fe62352 Gitweb: https://git.kernel.org/tip/02bea6ff684b62c14d5c6eafaee752d24= fe62352 Author: Caleb James DeLisle AuthorDate: Thu, 30 Apr 2026 16:41:56=20 Committer: Thomas Gleixner CommitterDate: Mon, 11 May 2026 15:29:30 +02:00 dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping In MIPS VEIC mode (Vectored External Interrupt Controller), the hardware stops directly dispatching CPU interrupts such as IPIs or CPU performance counters, and instead it communicates them to the external interrupt controller (the hardware described here) which prioritizes, renumbers, and integrates them with its own hardware interrupt pins. Interrupts from the external controller are then dispatched through a different method via a dispatch table. In effect, the external controller subsumes the CPU controller and becomes the root. 34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136 Since there are interrupts which ought to be controlled by the CPU controller driver - particularly the IPI interrupts - we create a reverse mapping where those interrupts may be sent back to the CPU intc when they are received. This maintains the fiction that there is still a hierarchy, and keeps the DT the same no matter whether the processor is in VEIC mode or not. The econet,cpu-interrupt-map is optional and if omitted, it's assumed that no interrupts need to be mapped. Signed-off-by: Caleb James DeLisle Signed-off-by: Thomas Gleixner Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260430164157.6026-2-cjd@cjdns.fr --- Documentation/devicetree/bindings/interrupt-controller/econet,en751221-int= c.yaml | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,= en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller= /econet,en751221-intc.yaml index 5536319..44c0978 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/econet,en75122= 1-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en75122= 1-intc.yaml @@ -52,6 +52,25 @@ properties: - description: primary per-CPU IRQ - description: shadow IRQ number =20 + econet,cpu-interrupt-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + When running in VEIC mode, the hardware re-routes interrupts from the + CPU interrupt controller core to the "external" interrupt controller + (this device). It then prioritizes them and sends them back to the C= PU + along with its own interrupts. The CPU hardware handles interrupts u= sing + a special dispatch table (the normal interrupt handler is not invoke= d). + In this interrupt controller, the CPU interrupts are renumbered as t= hey + are merged with this controller's own hardware interrupts. + + This is the inverse of an interrupt-map, mapping which interrupts fr= om + this controller must be routed back to the CPU interrupt domain for + correct handling there. + items: + items: + - description: The interrupt number as received in this controller + - description: The interrupt number to be dispatched on the CPU in= tc + required: - compatible - reg @@ -74,5 +93,6 @@ examples: interrupts =3D <2>; =20 econet,shadow-interrupts =3D <7 2>, <8 3>, <13 12>, <30 29>; + econet,cpu-interrupt-map =3D <7 0>, <8 1>; }; ...