From nobody Sat Jun 13 02:06:38 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 197083DA7F7; Mon, 11 May 2026 13:32:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778506358; cv=none; b=SKP2TeogaEGDneJ9C9yQQOwGscJFaI63PrjmKZFkB/mH0A5OqwfABO1vMDbuL/tqB5YAKokY0mtRvbZtlxAPEm/MZP77RykuhNv0kY9kwg2QEIOg7oxs+Fz31JezBbMFy6/1hO6l7n/oLOSqp5p5gbmvuGnKHtsH1S12RkedQqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778506358; c=relaxed/simple; bh=bs/GoaB3PgIEzcfQToJeGkVwu3mL1V/il0wz747Yn3s=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=ZMhcuF0TL9R6INUS/Ln/w9Fzqe7VGycOrqethW0sgmOFppWbB0dck9/40kIXxKmoXxr0LnF1/g9my3ZTJDRKJknv/Is2rtWwntVmkKpxgzcRVHEiWE95mU+hzP/vr1PzfUkb75eMW9H9KegUvs349oRFncveGpdVS+oNIxNte1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=q93KRbTU; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1vuv26M5; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="q93KRbTU"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1vuv26M5" Date: Mon, 11 May 2026 13:32:34 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1778506355; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cTX4qrUjxsLadv0rOHb4NNS7LUGa/NvZ1qgH4/1D7nk=; b=q93KRbTU90Ywu7ACm0JqPtxwwM8V0L6vmscp8qiHY2KYc3AOc5yNQ8/W08E7joI644fHSe 4KJt8MzUkAbhCFIK44Y6KshG4TV/v27GZyht+JQK0oGsGnC8ipcCX6vwfodJHQKi0+hA8J jOXYTmtepiDRjq/MGHQ9VeAyiDbmDm/1ROpVWfMk3Cxd+LE/eBKDMnWPpcku6es4EKHYa1 krCwALJ7DCiv3jG/zPO5T9BH4y4Ry9496LVO8ZGJSBVQK9p9Ev3aoiehW35H89E5PadLV5 3JnFfyNy7bOAaASOAO8I3C2kXE3H8DxUNbJgfmMOOfK26plT+YCj2sk2GGjfvQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1778506355; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cTX4qrUjxsLadv0rOHb4NNS7LUGa/NvZ1qgH4/1D7nk=; b=1vuv26M5Cf0II0z1eJAAB+Yv4rR4+zzQEsaULLqFl1BhAfaz5Kv/kXOzlKTeLaPaohWV3e aGpM0qwam6aohKCg== From: "tip-bot2 for Caleb James DeLisle" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/econet-en751221: Support MIPS 34Kc VEIC mode Cc: Caleb James DeLisle , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260430164157.6026-3-cjd@cjdns.fr> References: <20260430164157.6026-3-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177850635405.188840.14691065713329352190.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 2ee2a685ee838fd103a306dab43f6969b61e9156 Gitweb: https://git.kernel.org/tip/2ee2a685ee838fd103a306dab43f6969b= 61e9156 Author: Caleb James DeLisle AuthorDate: Thu, 30 Apr 2026 16:41:57=20 Committer: Thomas Gleixner CommitterDate: Mon, 11 May 2026 15:29:31 +02:00 irqchip/econet-en751221: Support MIPS 34Kc VEIC mode The Vectored External Interrupt Controller mode present in the MIPS 34Kc and 1004Kc variants causes the CPU to stop dispatching interrupts by the normal code path and instead it sends those interrupts to the external interrupt controller to be prioritized, renumbered, and sent back. When they come back, they are handled through a different path using a dispatch table, so plat_irq_dispatch() never sees action. This of course subverts the traditional intc hierarchy, and on the 1004Kc the interrupt controller is standardized (IRQ_GIC) so it can be reasonably considered part of the CPU itself - and tighter coupling between IRQ_GIC and arch/mips/* is tolerable. However on the 34Kc the intc is defined by each SoC vendor, so it's required to have a modular driver - but for a device which in fact ends up taking over the entire interrupt system. Let the DT describe which IRQs which come from the CPU and should be routed back and handled by the CPU intc. These particularly include the two IPI interrupts which would otherwise necessitate duplication of all the IPI supporting infrastructure from the CPU intc. Signed-off-by: Caleb James DeLisle Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260430164157.6026-3-cjd@cjdns.fr --- drivers/irqchip/irq-econet-en751221.c | 186 +++++++++++++++++++++++-- 1 file changed, 178 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-econet-en751221.c b/drivers/irqchip/irq-ec= onet-en751221.c index d83d5eb..2ca5d90 100644 --- a/drivers/irqchip/irq-econet-en751221.c +++ b/drivers/irqchip/irq-econet-en751221.c @@ -30,6 +30,8 @@ #include #include =20 +#include + #define IRQ_COUNT 40 =20 #define NOT_PERCPU 0xff @@ -41,15 +43,19 @@ #define REG_PENDING1 0x54 =20 /** - * @membase: Base address of the interrupt controller registers - * @interrupt_shadows: Array of all interrupts, for each value, - * - NOT_PERCPU: This interrupt is not per-cpu, so it has no shadow - * - IS_SHADOW: This interrupt is a shadow of another per-cpu interrupt - * - else: This is a per-cpu interrupt whose shadow is the value + * @membase: Base address of the interrupt controller registers + * @domain: The irq_domain for direct dispatch + * @ipi_domain: The irq_domain for inter-process dispatch + * @interrupt_shadows: Array of all interrupts, for each value, + * - NOT_PERCPU: This interrupt is not per-cpu, so it has no shadow + * - IS_SHADOW: This interrupt is a shadow of another per-cpu interrupt + * - else: This is a per-cpu interrupt whose shadow is the value */ static struct { - void __iomem *membase; - u8 interrupt_shadows[IRQ_COUNT]; + void __iomem *membase; + struct irq_domain *domain; + struct irq_domain *ipi_domain; + u8 interrupt_shadows[IRQ_COUNT]; } econet_intc __ro_after_init; =20 static DEFINE_RAW_SPINLOCK(irq_lock); @@ -150,6 +156,56 @@ static void econet_intc_from_parent(struct irq_desc *d= esc) chained_irq_exit(chip, desc); } =20 +/* + * When in VEIC mode, the CPU jumps to a handler in the vector table. + * The only way to know which interrupt is being triggered is from the vec= tor table offset that + * has been jumped to. Reading REG_PENDING(0|1) will tell you which interr= upts are currently + * pending in the intc, but that will not tell you which one the intc want= s you to process + * right now. And if you are not processing the exact interrupt that the i= ntc wants you to be + * processing, you might be on the wrong VPE. You can't tell which VPE any= given REG_PENDING + * interrupt is intended for (shadow IRQ numbers are for masking only, the= y never flag as + * pending). + * + * Consequently, this little ritual of generating n handler functions and = registering one per + * interrupt is unavoidable. + */ +#define X(irq) \ + static void econet_irq_dispatch ## irq (void) \ + { \ + do_domain_IRQ(econet_intc.domain, irq); \ + } + + X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7) X(8) X(9) +X(10) X(11) X(12) X(13) X(14) X(15) X(16) X(17) X(18) X(19) +X(20) X(21) X(22) X(23) X(24) X(25) X(26) X(27) X(28) X(29) +X(30) X(31) X(32) X(33) X(34) X(35) X(36) X(37) X(38) X(39) + +#undef X +#define X(irq) econet_irq_dispatch ## irq, + +static void (* const econet_irq_dispatchers[])(void) =3D { + X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7) X(8) X(9) + X(10) X(11) X(12) X(13) X(14) X(15) X(16) X(17) X(18) X(19) + X(20) X(21) X(22) X(23) X(24) X(25) X(26) X(27) X(28) X(29) + X(30) X(31) X(32) X(33) X(34) X(35) X(36) X(37) X(38) X(39) +}; + +/* Likewise, we do the same for the 2 IPI IRQs so that we can route them b= ack */ +static void econet_cpu_dispatch0(void) +{ + do_domain_IRQ(econet_intc.ipi_domain, 0); +} + +static void econet_cpu_dispatch1(void) +{ + do_domain_IRQ(econet_intc.ipi_domain, 1); +} + +static void (* const econet_cpu_dispatchers[])(void) =3D { + econet_cpu_dispatch0, + econet_cpu_dispatch1, +}; + static const struct irq_chip econet_irq_chip; =20 static int econet_intc_map(struct irq_domain *d, u32 irq, irq_hw_number_t = hwirq) @@ -174,6 +230,10 @@ static int econet_intc_map(struct irq_domain *d, u32 i= rq, irq_hw_number_t hwirq) } =20 irq_set_chip_data(irq, NULL); + + if (cpu_has_veic) + set_vi_handler(hwirq + 1, econet_irq_dispatchers[hwirq]); + return 0; } =20 @@ -249,6 +309,100 @@ static int __init get_shadow_interrupts(struct device= _node *node) return 0; } =20 +/** + * econet_cpu_init() - configure routing of CPU interrupts to the correct = domain. + * @node: The devicetree node of this interrupt controller. + * + * Interrupts that originate from the CPU are unconditionally unmasked her= e and are re-routed back + * to the IPI irq_domain in the CPU intc. Masking still takes place but th= e CPU intc is in charge + * of it, using the mask bits of the c0_status register. + * + * Note that because IP2 ... IP7 are repurposed as Interrupt Priority Leve= l, only the two IPI + * interrupts are actually supported. + */ +static int __init econet_cpu_init(struct device_node *node) +{ + const char *field =3D "econet,cpu-interrupt-map"; + struct device_node *parent_intc; + int map_size; + u32 mask; + + map_size =3D of_property_count_u32_elems(node, field); + + if (map_size <=3D 0) { + return 0; + } else if (map_size % 2) { + pr_err("%pOF: %s count is odd, ignoring\n", node, field); + return 0; + } + + u32 *maps __free(kfree) =3D kmalloc_array(map_size, sizeof(u32), GFP_KERN= EL); + if (!maps) + return -ENOMEM; + + if (of_property_read_u32_array(node, field, maps, map_size)) { + pr_err("%pOF: Failed to read %s\n", node, field); + return -EINVAL; + } + + /* Validation */ + for (int i =3D 0; i < map_size; i +=3D 2) { + u32 receive =3D maps[i]; + u32 dispatch =3D maps[i + 1]; + u8 shadow; + + if (receive >=3D IRQ_COUNT) { + pr_err("%pOF: Entry %d:%d in %s (%u) is out of bounds\n", + node, i, 0, field, receive); + return -EINVAL; + } + + shadow =3D econet_intc.interrupt_shadows[receive]; + if (shadow !=3D NOT_PERCPU && shadow >=3D IRQ_COUNT) { + pr_err("%pOF: Entry %d:%d in %s (%u) has invalid shadow (%d)\n", + node, i, 0, field, receive, shadow); + return -EINVAL; + } + + if (dispatch >=3D ARRAY_SIZE(econet_cpu_dispatchers)) { + pr_err("%pOF: Entry %d:%d in %s (%u) is out of bounds only IPI interrup= ts are supported\n", + node, i, 1, field, dispatch); + return -EINVAL; + } + } + + parent_intc =3D of_irq_find_parent(node); + if (!parent_intc) { + pr_err("%pOF: Failed to find parent %s\n", node, "IRQ device"); + return -ENODEV; + } + + econet_intc.ipi_domain =3D irq_find_matching_host(parent_intc, DOMAIN_BUS= _IPI); + if (!econet_intc.ipi_domain) { + pr_err("%pOF: Failed to find parent %s\n", node, "IPI domain"); + return -ENODEV; + } + + mask =3D 0; + for (int i =3D 0; i < map_size; i +=3D 2) { + u32 receive =3D maps[i]; + u32 dispatch =3D maps[i + 1]; + u8 shadow; + + set_vi_handler(receive + 1, econet_cpu_dispatchers[dispatch]); + + mask |=3D BIT(receive); + + shadow =3D econet_intc.interrupt_shadows[receive]; + if (shadow !=3D NOT_PERCPU) + mask |=3D BIT(shadow); + } + + econet_wreg(REG_MASK0, mask, mask); + + return 0; +} + static int __init econet_intc_of_init(struct device_node *node, struct dev= ice_node *parent) { struct irq_domain *domain; @@ -294,7 +448,23 @@ static int __init econet_intc_of_init(struct device_no= de *node, struct device_no goto err_unmap; } =20 - irq_set_chained_handler_and_data(irq, econet_intc_from_parent, domain); + /* + * 34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136: + * In VEIC mode, IP2 ... IP7 are repurposed as Interrupt Priority Level. = The controller + * will filter incoming interrupts whose priority is lower than the IPL n= umber. Therefore + * we must not set any of these bits. We avoid setting IP2 by not actuall= y chaining this + * intc to the CPU intc. + */ + if (cpu_has_veic) { + ret =3D econet_cpu_init(node); + + if (ret) + return ret; + } else { + irq_set_chained_handler_and_data(irq, econet_intc_from_parent, domain); + } + + econet_intc.domain =3D domain; =20 return 0; =20