From nobody Sat Jun 13 02:09:49 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93FBB3E5590; Mon, 11 May 2026 13:16:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778505389; cv=none; b=Q9ZJE2b//yKOQ3JtIBEXvjmwTu3dmHsLml1qpPL1pcWdAL75bzIrDLqyWN+1D4362Hxenvx7Ln7mzcE/qw/g0TdLownpzmAZ45MPUUA8V9uv6HJSFdaECV1f7qg8ozWAJPs2VTAdihC11Ja1F0RvAi17r3h9q9T1RntPhPOTveo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778505389; c=relaxed/simple; bh=lA7vtqPhX3uj1OvL3SYsnTamctTqur3uv5Zs5PWRMlg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=RGOlBiE7uqumcoO4+T3kI9G7mlyLn1niNha7SkV9gABuxj76fx63LFNsY0OmL7G86DUHgwv9kCLjnzMiAKw45LyRrPO4jeoQaXVPSKmOGgC4xc04/a6qJ64NTjBHrVYmQxaTYweT9eHvTUtzJvgqALPaWkUCB9G0mLGbTYOq9Zc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=U4q8bSwh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=uGeCgoG4; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="U4q8bSwh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uGeCgoG4" Date: Mon, 11 May 2026 13:16:23 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1778505384; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nVdqKSrGIMRWJsN3+QcLhGs/SCXkbnpvthblDpUsfEY=; b=U4q8bSwhUjH+AfHGiG5acRDxK0g+FTxwhUs9czSSeRoiwyDjWRaxg8dF+VbE8ktLQ7g7Zr cCymoFabaL8phhUfo71nq0+/SunF+uqB8KGBzcrSyJENVQ4A5k3rx1jd8EjVuwOvhsOAoh L3k8ZFfnct3VMyNTlLwguLt6ZIWlqC47RZoUIKNmav5fmF1z/6HToQ2Q731geShCmNrRmT ZtIGbkcCnqu6bRuyRRggY0AzDX0AHh+FNJbVKYd7UOojLu0mCz2xwWL0fS16SO7VByTcsN 7TiRY7JZRzttl+gucmor2z9pPHpoSI/sPvbKbWoZWzc3wA7y8Zf8WOvV9qRgfg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1778505384; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nVdqKSrGIMRWJsN3+QcLhGs/SCXkbnpvthblDpUsfEY=; b=uGeCgoG4FH5faGmDHR3VNsQAnIgvHYOaRXugonvZybZ/Ztm0rNDALyzGlnoekcdCbScRZr vSHeziln38NxZYCA== From: "tip-bot2 for Xianwei Zhao" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/meson-gpio: Add support for Amlogic A9 SoCs Cc: Xianwei Zhao , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260508-a9-gpio-irqchip-v1-3-9dc5f3e022e0@amlogic.com> References: <20260508-a9-gpio-irqchip-v1-3-9dc5f3e022e0@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177850538321.188840.13072833368882954220.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 5b9cb104594f0ea73c2eba83aa93c0cb7ac2238e Gitweb: https://git.kernel.org/tip/5b9cb104594f0ea73c2eba83aa93c0cb7= ac2238e Author: Xianwei Zhao AuthorDate: Fri, 08 May 2026 07:36:56=20 Committer: Thomas Gleixner CommitterDate: Mon, 11 May 2026 15:11:29 +02:00 irqchip/meson-gpio: Add support for Amlogic A9 SoCs The Amlogic A9 SoCs supports the following GPIO interrupt lines: A9 IRQ Number: - 95:86 10 pins on bank Y - 85:84 2 pins on bank CC - 83:64 20 pins on bank A - 63:48 16 pins on bank Z - 47:30 18 pins on bank X - 29:22 8 pins on bank H - 21:14 8 pins on bank M - 13:0 14 pins on bank B A9 AO IRQ Number: - 38 1 pins on bank TESTN - 37:31 7 pins on bank C - 30:13 18 pins on bank D - 12:0 13 pins on bank AO Update the driver to handle these variants. Signed-off-by: Xianwei Zhao Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-3-9dc5f3e022e0@a= mlogic.com --- drivers/irqchip/irq-meson-gpio.c | 77 +++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index 74a376e..91a9c33 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -27,6 +27,10 @@ /* use for A1 like chips */ #define REG_PIN_A1_SEL 0x04 =20 +/* use for A9 like chips */ +#define REG_A9_AO_POL 0x00 +#define REG_A9_AO_EDGE 0x30 + /* * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by * bits 24 to 31. Tests on the actual HW show that these bits are @@ -53,6 +57,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_i= rq_controller *ctl, static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, unsigned int type, u32 *channel_hwirq); +static int meson_a9_ao_gpio_irq_set_type(struct meson_gpio_irq_controller = *ctl, + unsigned int type, u32 *channel_hwirq); static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ct= l, unsigned int type, u32 *channel_hwirq); =20 @@ -116,6 +122,18 @@ struct meson_gpio_irq_params { .pin_sel_mask =3D 0xff, \ .nr_channels =3D 2, \ =20 +#define INIT_MESON_A9_AO_COMMON_DATA(irqs) \ + INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ + meson_a1_gpio_irq_sel_pin, \ + meson_a9_ao_gpio_irq_set_type) \ + .support_edge_both =3D true, \ + .edge_both_offset =3D 0, \ + .edge_single_offset =3D 0, \ + .edge_pol_reg =3D 0x2c, \ + .pol_low_offset =3D 0, \ + .pin_sel_mask =3D 0xff, \ + .nr_channels =3D 20, \ + #define INIT_MESON_S4_COMMON_DATA(irqs) \ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ meson_a1_gpio_irq_sel_pin, \ @@ -170,6 +188,14 @@ static const struct meson_gpio_irq_params a5_params = =3D { INIT_MESON_S4_COMMON_DATA(99) }; =20 +static const struct meson_gpio_irq_params a9_params =3D { + INIT_MESON_S4_COMMON_DATA(96) +}; + +static const struct meson_gpio_irq_params a9_ao_params =3D { + INIT_MESON_A9_AO_COMMON_DATA(39) +}; + static const struct meson_gpio_irq_params s4_params =3D { INIT_MESON_S4_COMMON_DATA(82) }; @@ -203,6 +229,8 @@ static const struct of_device_id meson_irq_gpio_matches= [] __maybe_unused =3D { { .compatible =3D "amlogic,a4-gpio-ao-intc", .data =3D &a4_ao_params }, { .compatible =3D "amlogic,a4-gpio-intc", .data =3D &a4_params }, { .compatible =3D "amlogic,a5-gpio-intc", .data =3D &a5_params }, + { .compatible =3D "amlogic,a9-gpio-ao-intc", .data =3D &a9_ao_params }, + { .compatible =3D "amlogic,a9-gpio-intc", .data =3D &a9_params }, { .compatible =3D "amlogic,s6-gpio-intc", .data =3D &s6_params }, { .compatible =3D "amlogic,s7-gpio-intc", .data =3D &s7_params }, { .compatible =3D "amlogic,s7d-gpio-intc", .data =3D &s7_params }, @@ -376,6 +404,55 @@ static int meson8_gpio_irq_set_type(struct meson_gpio_= irq_controller *ctl, } =20 /* + * gpio irq relative registers for a9_ao + * -PADCTRL_GPIO_IRQ_CTRL0 + * bit[31]: enable/disable all the irq lines + * bit[0-19]: polarity trigger + * + * -PADCTRL_GPIO_IRQ_CTRL[X] + * bit[0-5]: 6 bits to choose gpio source for irq line 2*[X] - 2 + * bit[16-21]:6 bits to choose gpio source for irq line 2*[X] - 1 + * where X =3D 1-10 + * + * -PADCTRL_GPIO_IRQ_CTRL[11] + * bit[0-19]: both edge trigger + * + * -PADCTRL_GPIO_IRQ_CTRL[12] + * bit[0-19]: single edge trigger + */ +static int meson_a9_ao_gpio_irq_set_type(struct meson_gpio_irq_controller = *ctl, + unsigned int type, u32 *channel_hwirq) +{ + const struct meson_gpio_irq_params *params =3D ctl->params; + unsigned int idx; + u32 val; + + idx =3D meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); + + type &=3D IRQ_TYPE_SENSE_MASK; + + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0); + + if (type =3D=3D IRQ_TYPE_EDGE_BOTH) { + val =3D BIT(ctl->params->edge_both_offset + idx); + meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, val, val); + return 0; + } + + val =3D 0; + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) + val =3D BIT(idx); + meson_gpio_irq_update_bits(ctl, REG_A9_AO_POL, BIT(idx), val); + + val =3D 0; + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + val =3D BIT(idx); + meson_gpio_irq_update_bits(ctl, REG_A9_AO_EDGE, BIT(idx), val); + + return 0; +}; + +/* * gpio irq relative registers for s4 * -PADCTRL_GPIO_IRQ_CTRL0 * bit[31]: enable/disable all the irq lines