From nobody Sat Jun 13 02:07:31 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1B813BADAA; Mon, 11 May 2026 13:11:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778505062; cv=none; b=fj9SiEpGRZcCxTFpzJnUs2KED8Lfgs+O7j8DD0HZldDGsg9vE2ZXtBi6oVOeUnEonx16ROvGUYpd7sOohrigSymG7LVuvU5lcaFvfJyV0Jej1d54ShoeLdU/PuM0xYhK2dnade9dZ3LHCeE0x6/NbozTLAb51Zr17cNNTdtqIf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778505062; c=relaxed/simple; bh=VYYjE8WYbSPL6AKTkakiXuv1Prwzl4MO47DfAwQRPWA=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=TLueLdZE59wqNHu1P7mDNF8Pg7ezSUNf0dbgsh32oTVUJ3aML0Dx/hJnUz7Tv3jTqFwO8/SCne8/8Nf2UbG2OhfHVfCZbY60us6tsQGL/rH+zcKxAimSC43ojBr1T+C+d+azAlMIuZHNgqmN1nJmRC9ZvSzO41PSAhF6OrnLTVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ltsQW+yJ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=xzEWggsg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ltsQW+yJ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xzEWggsg" Date: Mon, 11 May 2026 13:10:57 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1778505059; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WYBHUIPquzb2RFImw9Amt6KP092rLc5UgHU6mKI+zzA=; b=ltsQW+yJ/oHEKmFEsDEAMxgmPQcqd1AwOBg1EcqI0bH923gtX5ew4O/uYLreUb0O6NfeWh /DKPZTb/P3IhH1ycSxlVkq/XsqjdGN6weJlU1f1b6xBId1A3PwpVOPmBNtTXXVQBZOJdva Ru77QaeN0lhWqJw9zR+nUZvgdtYeG7ksxTvZumUqnOEhYYM4peAq0muKQ0NBN77kWp0xVM 1ma79zzpkVj15p85vme9wueN22vVPHHwqtlF3ETQqT8y49zE/AHZsz+5mlhKjMIdlfjp03 XpY5UoCvMYQG5sDIyKm4NZ52ZYGmmtFZExxdm0vgWLe0UV+y20To4/bwh0YYwg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1778505059; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WYBHUIPquzb2RFImw9Amt6KP092rLc5UgHU6mKI+zzA=; b=xzEWggsgaLd4SkZx4VpWNFbjtc3rzkoHrpP9kvWYKv7xesHi5SWMVKk/J9JwaZOvt1X9nc tqex4Y6bcROC/2CA== From: "tip-bot2 for Xianwei Zhao" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/urgent] irqchip/meson-gpio: Use the correct register in meson_s4_gpio_irq_set_type() Cc: Xianwei Zhao , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@amlogic.com> References: <20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177850505797.188840.17262117885217269972.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/urgent branch of tip: Commit-ID: e8d3dcdf9f576c7527f0a088b953abfaa601ae68 Gitweb: https://git.kernel.org/tip/e8d3dcdf9f576c7527f0a088b953abfaa= 601ae68 Author: Xianwei Zhao AuthorDate: Fri, 08 May 2026 07:36:54=20 Committer: Thomas Gleixner CommitterDate: Mon, 11 May 2026 15:06:48 +02:00 irqchip/meson-gpio: Use the correct register in meson_s4_gpio_irq_set_type() meson_s4_gpio_irq_set_type() uses the both-edge trigger register for configuring level type and single edge mode interrupts, which is not correct. Use REG_EDGE_POL instead. Fixes: bbd6fcc76b39 ("irqchip: Add support for Amlogic A4 and A5 SoCs") Signed-off-by: Xianwei Zhao Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@a= mlogic.com --- drivers/irqchip/irq-meson-gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-g= pio.c index f722e9c..74a376e 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -415,8 +415,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio= _irq_controller *ctl, if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) val |=3D BIT(ctl->params->edge_single_offset + idx); =20 - meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, - BIT(idx) | BIT(12 + idx), val); + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(idx) | BIT(12 + idx), v= al); return 0; }; =20