From nobody Sat Jun 13 18:12:12 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39AE130C617; Wed, 6 May 2026 06:16:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778048214; cv=none; b=s+rX7zPTHMyWbLxBuyh+doUpYjfVZGnF3+VyEQsOIfatd/OVLLE2cmeXC4EbVnobd8x8EOMb7W2BnNXAM5fq344HnMnmtzjP5uykbaXiDMj1Bdj6Ryi2t3w99LsQuLXvqnW2fjYEF61A3OZLub8EZNFWasYosPHT2Iyu3qRhauE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778048214; c=relaxed/simple; bh=t/PfsJl8nCNhd5RCtTEyxaQHjZ6IqTr/+7M98qFWef8=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=OCkT7p0oLwlbKK0a0kZTsMdpF8lxT0gaBeeqBEo6tqSSzNL0mcv6I8GCkATyZ4re+pVCkkMAgrYoEQs34rW4bkTbdRgLchzqaIABUSLPB2PhuqJnac0CbLr/mogydCIA5KAu16HH2H1i5kM8WmOdqeLVVPGdAPMeHrTSxOx9IVA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1Wts/31C; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=u55hw8K5; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1Wts/31C"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="u55hw8K5" Date: Wed, 06 May 2026 06:16:50 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1778048211; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=nCUkpBnoLOKZnXcEhb2sjNYRXJgHznmaf/Yrg15rt3g=; b=1Wts/31CtHbRSp6v1zOQKY/ZQeACjVYm58dLn2UhmLP0UI+HzxC+UaMjXPO904ZbijtLXF EiNaA3nGNBWPfDaBiAoxz/XljJoHJiqPkNJJYT+BVYXKiEynnlfORD3fYobwDN+UzJ6hfc +Fx6U2B5ai9OhNw29wm4CEa10QA1067/UlGrxa31XSSWXFve/u4IdahucEtVMaOhW3Zp6n QfLRZ40qawVUi68AzSayn8lpw5V2f7i0W4CpTJdSdvHFa059onQzghrSKhlNjZ+LMUkCrK V85GXnUln/bSLnDXwADdFQNe81GCYwchvJ0h2aI24Vh1IpqhklitBdukxr4jGg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1778048211; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=nCUkpBnoLOKZnXcEhb2sjNYRXJgHznmaf/Yrg15rt3g=; b=u55hw8K5QdVCyqH7vm4XlH/03Z51aRcseY2Fqkjv3qcC9bLMeqa5RB9poYzLpISOcEcN63 tyFjCpo4s7f4a5CA== From: "tip-bot2 for Ingo Molnar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/cpu: Remove CPU_SUP_UMC_32 support Cc: Ingo Molnar , Arnd Bergmann , Dave Hansen , Linus Torvalds , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177804821034.424702.17318872308538821525.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 7d328c5de43a9e29dc6cd1ba3e578c1a32ebc486 Gitweb: https://git.kernel.org/tip/7d328c5de43a9e29dc6cd1ba3e578c1a3= 2ebc486 Author: Ingo Molnar AuthorDate: Fri, 25 Apr 2025 10:42:00 +02:00 Committer: Ingo Molnar CommitterDate: Wed, 06 May 2026 08:01:45 +02:00 x86/cpu: Remove CPU_SUP_UMC_32 support These are 486 based CPUs, which build option (M486) is now gone upstream. Signed-off-by: Ingo Molnar Reviewed-by: Arnd Bergmann Acked-by: Dave Hansen Cc: Linus Torvalds Link: https://lore.kernel.org/r/20250425084216.3913608-4-mingo@kernel.org --- arch/x86/Kconfig.cpu | 14 -------------- arch/x86/kernel/cpu/umc.c | 26 -------------------------- 2 files changed, 40 deletions(-) delete mode 100644 arch/x86/kernel/cpu/umc.c diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 8868aa1..71f2644 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -399,20 +399,6 @@ config CPU_SUP_TRANSMETA_32 =20 If unsure, say N. =20 -config CPU_SUP_UMC_32 - default y - bool "Support UMC processors" if PROCESSOR_SELECT - depends on M486SX || M486 || (EXPERT && !64BIT) - help - This enables detection, tunings and quirks for UMC processors - - You need this enabled if you want your kernel to run on a - UMC CPU. Disabling this option on other types of CPUs - makes the kernel a tiny bit smaller. Disabling it on a UMC - CPU might render the kernel unbootable. - - If unsure, say N. - config CPU_SUP_ZHAOXIN default y bool "Support Zhaoxin processors" if PROCESSOR_SELECT diff --git a/arch/x86/kernel/cpu/umc.c b/arch/x86/kernel/cpu/umc.c deleted file mode 100644 index 65a58a3..0000000 --- a/arch/x86/kernel/cpu/umc.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include "cpu.h" - -/* - * UMC chips appear to be only either 386 or 486, - * so no special init takes place. - */ - -static const struct cpu_dev umc_cpu_dev =3D { - .c_vendor =3D "UMC", - .c_ident =3D { "UMC UMC UMC" }, - .legacy_models =3D { - { .family =3D 4, .model_names =3D - { - [1] =3D "U5D", - [2] =3D "U5S", - } - }, - }, - .c_x86_vendor =3D X86_VENDOR_UMC, -}; - -cpu_dev_register(umc_cpu_dev); -