From nobody Sat Jun 13 23:10:49 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16C003803D4; Tue, 5 May 2026 10:50:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777978203; cv=none; b=qcrK13WwITbWAY5Cjj+3zSJibQENgATwSB5xnA8cbLg9T0mF4H3/GsxGIs7RiBRAe4UHbOXhE7PbLu11XYh9nHYieh09CPPP37h/SwkPF1L9KvHfXhleFsJq74WkAnzYrQSf6wtujH52sWS07aEVGHI3/9o9HhICBHrnz7CaxS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777978203; c=relaxed/simple; bh=VRV3eA0qGkd7EUytyHDlw6+vqgToPi9iTl2nDqOFoDg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=rw3CrBBkft+LOCRYtYGeUA0ENIEjngBcnDaiSvskTvU0fqBOsP98xgAjigzaeDTQ0riYC8L/9TCMzVaOY41k/+d1G1CWstWyoAxo7e7H19Ou3GRjrm8qKL/W6Dr9J0nuA+Y9qOzpSb3a8b4O6hs1z/p5jTqNi8AztdO++O+9ulc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rDxhhAub; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=y1so6JnJ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rDxhhAub"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="y1so6JnJ" Date: Tue, 05 May 2026 10:49:56 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1777978198; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MZwOHM9G0CWN8/jvwHFKK6N78xKUBf4rKf6i58WSkCA=; b=rDxhhAubMHrRF17e1McK6czir+TuB1ea6kDL0/73U1uYbA0wATgXdQ3/ktr0LJNe9wg2z3 ZyJZ6avfWIot07oYXzkE4FJpWSrYiaiND6VsMqttW6W+fvzl6T6AXoZz/MsDDT0Ki8cM6E TZLuv8Vcj4xfQJwH5/ZSLVkpd16xDxXtXNcOM1ruKHVCjRfQs/p0s/6EotnrEUgYxrxa2m xIoAlnWMneGFo6JvBv+z9vw4L30J6HFOu6KugrN/xRSU7PZJRINsqEgCZ2+AS5W2u/FLt5 St2YuG26Tkg6l8HzxJn1TFvjtiwYi9HrMf8DUwhs49Xtj0CoP4Eh6uREiujQyA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1777978198; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MZwOHM9G0CWN8/jvwHFKK6N78xKUBf4rKf6i58WSkCA=; b=y1so6JnJ4pvgCmVgQGlhssjHlAbMVNrJ0oci12usgwRyrORYtMuz0WRtOW43Qg+gEXv4Mo +Bd0x5tCvLDxoBDg== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260430002558.712334-6-dapeng1.mi@linux.intel.com> References: <20260430002558.712334-6-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177797819674.424702.8102756366716929944.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 5c3cdc74af25fc7f64a3ed260b4f6eb8313a3b75 Gitweb: https://git.kernel.org/tip/5c3cdc74af25fc7f64a3ed260b4f6eb83= 13a3b75 Author: Dapeng Mi AuthorDate: Thu, 30 Apr 2026 08:25:58 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 05 May 2026 12:47:24 +02:00 perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C MSRs to configure event behavior. Currently, the driver maintains two independent variables acr_cfg_c and cfg_c_val to cache the values intended for these MSRs. Using separate variables to track a single hardware register state is error-prone and can lead to configuration conflicts. Consolidate the tracking into a single cfg_c_val variable to ensure a unified and consistent view of the PERF_CFG_C MSR state. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260430002558.712334-6-dapeng1.mi@linux.int= el.com --- arch/x86/events/intel/core.c | 13 +++++++------ arch/x86/events/perf_event.h | 4 +--- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index dd1e3aa..2b05587 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3169,10 +3169,10 @@ static void intel_pmu_config_acr(int idx, u64 mask,= u32 reload) wrmsrl(msr_b + msr_offset, mask); cpuc->acr_cfg_b[idx] =3D mask; } - /* Only need to update the reload value when there is a valid config valu= e. */ - if (mask && cpuc->acr_cfg_c[idx] !=3D reload) { + /* Only update CFG_C reload when ACR is actively enabled (mask !=3D 0) */ + if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) !=3D reload)) { wrmsrl(msr_c + msr_offset, reload); - cpuc->acr_cfg_c[idx] =3D reload; + cpuc->cfg_c_val[idx] =3D reload; } } =20 @@ -3198,14 +3198,15 @@ static void intel_pmu_enable_event_ext(struct perf_= event *event) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct hw_perf_event *hwc =3D &event->hw; - union arch_pebs_index old, new; - struct arch_pebs_cap cap; u64 ext =3D 0; =20 - cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + if (is_acr_event_group(event)) + ext |=3D (-hwc->sample_period) & ARCH_PEBS_RELOAD; =20 if (event->attr.precise_ip) { u64 pebs_data_cfg =3D intel_get_arch_pebs_data_config(event); + struct arch_pebs_cap cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + union arch_pebs_index old, new; =20 ext |=3D ARCH_PEBS_EN; if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 524668d..40d6fe0 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -322,10 +322,8 @@ struct cpu_hw_events { u64 fixed_ctrl_val; u64 active_fixed_ctrl_val; =20 - /* Intel ACR configuration */ + /* Intel ACR/arch-PEBS configuration */ u64 acr_cfg_b[X86_PMC_IDX_MAX]; - u64 acr_cfg_c[X86_PMC_IDX_MAX]; - /* Cached CFG_C values */ u64 cfg_c_val[X86_PMC_IDX_MAX]; =20 /*