From nobody Tue Jun 16 17:03:59 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 150483D6663; Thu, 30 Apr 2026 10:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777546610; cv=none; b=clKJ8nPtGwo+K/kiFbDJZkgMYVAc6B/LnGlMjhPMB19+Q7Pj5kr8A+7MgNzjyQXU7foXuYcKuVZdUitz46bI4MYqatVtYsnZV7DPDDFiS6vhMAMq8CowNyGs/mnU/3Y4Zrnqg4i1jpmAvvIhFjui943xw9P2mdLDzDi1sTDSp+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777546610; c=relaxed/simple; bh=zWGMM5gV2fOgTm1/LLTj4LqQMsOwqkZPIlk5MQ+iNwE=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Xo+sVbeeWmb+LPsaNZQNNsO9LgXluysoW5qeMMmTWg4mXBA46rUCHA2xsjwlIEL/CV4oxujdKmA5x6NSWBWXhalUg3xL1ntEpe9QVlwqGgWFjvRN/joHFOqJ9ZkoseIOpDE0xbGkMW0r5kP5hCfoixGRudKY7SNrip7Irf5DOmo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=t4gFmBDm; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=md4HdmvV; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="t4gFmBDm"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="md4HdmvV" Date: Thu, 30 Apr 2026 10:56:44 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1777546606; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FVVIBeidsFeLDhFBZC1Ur9iwKfwxxjN8iA0Dvt/BvSA=; b=t4gFmBDmt0w/pelfgz9mS1WqnGcuefgbvfwhgkCS0gUNHLuREh7jDqcWC+KYlTO5qKw2Pf qaUHfIiX0Eafb6ZPg1xV6sJQqQpZC+PVjn+iDkZsNXY8sMtMfuVAMzKmpmOK0zcT0hl7O/ MlYng2/uZYCJaxk8zUGbG/TMZ1rDv1ZumxNRf8d1jgv/OiDNDfT3KoJyMWF4d3Sn5xGfLb Wem+sn02H1NsPstlahtZMwBn3JvYAHIsDdAQQoZE+BLv82Yks0dY7khOt07FZVpOssf+Co iRo3JXxXDj/e9h3NeMTdigyjgBL0I2O2F4rHQ74aQuzkUcTnISj4I1eSCMAcfA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1777546606; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FVVIBeidsFeLDhFBZC1Ur9iwKfwxxjN8iA0Dvt/BvSA=; b=md4HdmvV26QBaHORJzCnElWESLEfFc0IGzZJkriAqoAXNOPTouHtAylxM0NfNkW5LAnvcg RvQfjRIBbcBxtaAg== From: "tip-bot2 for Changhuang Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/starfive: Rename jh8100 to jhb100 Cc: Changhuang Liang , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260416064751.632138-3-changhuang.liang@starfivetech.com> References: <20260416064751.632138-3-changhuang.liang@starfivetech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177754660452.3521451.18083295414641513317.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: ac2005bba8d938c03c3856a96f20afaa42002635 Gitweb: https://git.kernel.org/tip/ac2005bba8d938c03c3856a96f20afaa4= 2002635 Author: Changhuang Liang AuthorDate: Wed, 15 Apr 2026 23:47:48 -07:00 Committer: Thomas Gleixner CommitterDate: Thu, 30 Apr 2026 12:53:05 +02:00 irqchip/starfive: Rename jh8100 to jhb100 The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the driver file, Kconfig symbol, and internal references from "jh8100" to "jhb100" to accurately reflect the supported hardware. Signed-off-by: Changhuang Liang Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260416064751.632138-3-changhuang.liang@sta= rfivetech.com --- MAINTAINERS | 4 +- drivers/irqchip/Kconfig | 6 +- drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-starfive-jh8100-intc.c | 207 +-------------------- drivers/irqchip/irq-starfive-jhb100-intc.c | 207 ++++++++++++++++++++- 5 files changed, 213 insertions(+), 213 deletions(-) delete mode 100644 drivers/irqchip/irq-starfive-jh8100-intc.c create mode 100644 drivers/irqchip/irq-starfive-jhb100-intc.c diff --git a/MAINTAINERS b/MAINTAINERS index 30626d0..73af7d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25533,11 +25533,11 @@ F: Documentation/devicetree/bindings/phy/starfive= ,jh7110-usb-phy.yaml F: drivers/phy/starfive/phy-jh7110-pcie.c F: drivers/phy/starfive/phy-jh7110-usb.c =20 -STARFIVE JH8100 EXTERNAL INTERRUPT CONTROLLER DRIVER +STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-= intc.yaml -F: drivers/irqchip/irq-starfive-jh8100-intc.c +F: drivers/irqchip/irq-starfive-jhb100-intc.c =20 STATIC BRANCH/CALL M: Peter Zijlstra diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 387beef..35a1f65 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -677,13 +677,13 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP =20 -config STARFIVE_JH8100_INTC - bool "StarFive JH8100 External Interrupt Controller" +config STARFIVE_JHB100_INTC + bool "StarFive JHB100 External Interrupt Controller" depends on ARCH_STARFIVE || COMPILE_TEST default ARCH_STARFIVE select IRQ_DOMAIN_HIERARCHY help - This enables support for the INTC chip found in StarFive JH8100 + This enables support for the INTC chip found in StarFive JHB100 SoC. =20 If you don't know what to do here, say Y. diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 3d02441..d8da7c4 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -109,7 +109,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi= .o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_RISCV_RPMI_SYSMSI) +=3D irq-riscv-rpmi-sysmsi.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o -obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o +obj-$(CONFIG_STARFIVE_JHB100_INTC) +=3D irq-starfive-jhb100-intc.o obj-$(CONFIG_ACLINT_SSWI) +=3D irq-aclint-sswi.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o diff --git a/drivers/irqchip/irq-starfive-jh8100-intc.c b/drivers/irqchip/i= rq-starfive-jh8100-intc.c deleted file mode 100644 index bb62ef3..0000000 --- a/drivers/irqchip/irq-starfive-jh8100-intc.c +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * StarFive JH8100 External Interrupt Controller driver - * - * Copyright (C) 2023 StarFive Technology Co., Ltd. - * - * Author: Changhuang Liang - */ - -#define pr_fmt(fmt) "irq-starfive-jh8100: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define STARFIVE_INTC_SRC0_CLEAR 0x10 -#define STARFIVE_INTC_SRC0_MASK 0x14 -#define STARFIVE_INTC_SRC0_INT 0x1c - -#define STARFIVE_INTC_SRC_IRQ_NUM 32 - -struct starfive_irq_chip { - void __iomem *base; - struct irq_domain *domain; - raw_spinlock_t lock; -}; - -static void starfive_intc_bit_set(struct starfive_irq_chip *irqc, - u32 reg, u32 bit_mask) -{ - u32 value; - - value =3D ioread32(irqc->base + reg); - value |=3D bit_mask; - iowrite32(value, irqc->base + reg); -} - -static void starfive_intc_bit_clear(struct starfive_irq_chip *irqc, - u32 reg, u32 bit_mask) -{ - u32 value; - - value =3D ioread32(irqc->base + reg); - value &=3D ~bit_mask; - iowrite32(value, irqc->base + reg); -} - -static void starfive_intc_unmask(struct irq_data *d) -{ - struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); - - raw_spin_lock(&irqc->lock); - starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); - raw_spin_unlock(&irqc->lock); -} - -static void starfive_intc_mask(struct irq_data *d) -{ - struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); - - raw_spin_lock(&irqc->lock); - starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); - raw_spin_unlock(&irqc->lock); -} - -static struct irq_chip intc_dev =3D { - .name =3D "StarFive JH8100 INTC", - .irq_unmask =3D starfive_intc_unmask, - .irq_mask =3D starfive_intc_mask, -}; - -static int starfive_intc_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - irq_domain_set_info(d, irq, hwirq, &intc_dev, d->host_data, - handle_level_irq, NULL, NULL); - - return 0; -} - -static const struct irq_domain_ops starfive_intc_domain_ops =3D { - .xlate =3D irq_domain_xlate_onecell, - .map =3D starfive_intc_map, -}; - -static void starfive_intc_irq_handler(struct irq_desc *desc) -{ - struct starfive_irq_chip *irqc =3D irq_data_get_irq_handler_data(&desc->i= rq_data); - struct irq_chip *chip =3D irq_desc_get_chip(desc); - unsigned long value; - int hwirq; - - chained_irq_enter(chip, desc); - - value =3D ioread32(irqc->base + STARFIVE_INTC_SRC0_INT); - while (value) { - hwirq =3D ffs(value) - 1; - - generic_handle_domain_irq(irqc->domain, hwirq); - - starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); - starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); - - __clear_bit(hwirq, &value); - } - - chained_irq_exit(chip, desc); -} - -static int starfive_intc_probe(struct platform_device *pdev, struct device= _node *parent) -{ - struct device_node *intc =3D pdev->dev.of_node; - struct starfive_irq_chip *irqc; - struct reset_control *rst; - struct clk *clk; - int parent_irq; - int ret; - - irqc =3D kzalloc_obj(*irqc); - if (!irqc) - return -ENOMEM; - - irqc->base =3D of_iomap(intc, 0); - if (!irqc->base) { - pr_err("Unable to map registers\n"); - ret =3D -ENXIO; - goto err_free; - } - - rst =3D of_reset_control_get_exclusive(intc, NULL); - if (IS_ERR(rst)) { - pr_err("Unable to get reset control %pe\n", rst); - ret =3D PTR_ERR(rst); - goto err_unmap; - } - - clk =3D of_clk_get(intc, 0); - if (IS_ERR(clk)) { - pr_err("Unable to get clock %pe\n", clk); - ret =3D PTR_ERR(clk); - goto err_reset_put; - } - - ret =3D reset_control_deassert(rst); - if (ret) - goto err_clk_put; - - ret =3D clk_prepare_enable(clk); - if (ret) - goto err_reset_assert; - - raw_spin_lock_init(&irqc->lock); - - irqc->domain =3D irq_domain_create_linear(of_fwnode_handle(intc), STARFIV= E_INTC_SRC_IRQ_NUM, - &starfive_intc_domain_ops, irqc); - if (!irqc->domain) { - pr_err("Unable to create IRQ domain\n"); - ret =3D -EINVAL; - goto err_clk_disable; - } - - parent_irq =3D of_irq_get(intc, 0); - if (parent_irq < 0) { - pr_err("Failed to get main IRQ: %d\n", parent_irq); - ret =3D parent_irq; - goto err_remove_domain; - } - - irq_set_chained_handler_and_data(parent_irq, starfive_intc_irq_handler, - irqc); - - pr_info("Interrupt controller register, nr_irqs %d\n", - STARFIVE_INTC_SRC_IRQ_NUM); - - return 0; - -err_remove_domain: - irq_domain_remove(irqc->domain); -err_clk_disable: - clk_disable_unprepare(clk); -err_reset_assert: - reset_control_assert(rst); -err_clk_put: - clk_put(clk); -err_reset_put: - reset_control_put(rst); -err_unmap: - iounmap(irqc->base); -err_free: - kfree(irqc); - return ret; -} - -IRQCHIP_PLATFORM_DRIVER_BEGIN(starfive_intc) -IRQCHIP_MATCH("starfive,jh8100-intc", starfive_intc_probe) -IRQCHIP_PLATFORM_DRIVER_END(starfive_intc) - -MODULE_DESCRIPTION("StarFive JH8100 External Interrupt Controller"); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Changhuang Liang "); diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/i= rq-starfive-jhb100-intc.c new file mode 100644 index 0000000..2c9cdad --- /dev/null +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 External Interrupt Controller driver + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + */ + +#define pr_fmt(fmt) "irq-starfive-jhb100: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STARFIVE_INTC_SRC0_CLEAR 0x10 +#define STARFIVE_INTC_SRC0_MASK 0x14 +#define STARFIVE_INTC_SRC0_INT 0x1c + +#define STARFIVE_INTC_SRC_IRQ_NUM 32 + +struct starfive_irq_chip { + void __iomem *base; + struct irq_domain *domain; + raw_spinlock_t lock; +}; + +static void starfive_intc_bit_set(struct starfive_irq_chip *irqc, + u32 reg, u32 bit_mask) +{ + u32 value; + + value =3D ioread32(irqc->base + reg); + value |=3D bit_mask; + iowrite32(value, irqc->base + reg); +} + +static void starfive_intc_bit_clear(struct starfive_irq_chip *irqc, + u32 reg, u32 bit_mask) +{ + u32 value; + + value =3D ioread32(irqc->base + reg); + value &=3D ~bit_mask; + iowrite32(value, irqc->base + reg); +} + +static void starfive_intc_unmask(struct irq_data *d) +{ + struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + + raw_spin_lock(&irqc->lock); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); + raw_spin_unlock(&irqc->lock); +} + +static void starfive_intc_mask(struct irq_data *d) +{ + struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + + raw_spin_lock(&irqc->lock); + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); + raw_spin_unlock(&irqc->lock); +} + +static struct irq_chip intc_dev =3D { + .name =3D "StarFive JHB100 INTC", + .irq_unmask =3D starfive_intc_unmask, + .irq_mask =3D starfive_intc_mask, +}; + +static int starfive_intc_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_domain_set_info(d, irq, hwirq, &intc_dev, d->host_data, + handle_level_irq, NULL, NULL); + + return 0; +} + +static const struct irq_domain_ops starfive_intc_domain_ops =3D { + .xlate =3D irq_domain_xlate_onecell, + .map =3D starfive_intc_map, +}; + +static void starfive_intc_irq_handler(struct irq_desc *desc) +{ + struct starfive_irq_chip *irqc =3D irq_data_get_irq_handler_data(&desc->i= rq_data); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned long value; + int hwirq; + + chained_irq_enter(chip, desc); + + value =3D ioread32(irqc->base + STARFIVE_INTC_SRC0_INT); + while (value) { + hwirq =3D ffs(value) - 1; + + generic_handle_domain_irq(irqc->domain, hwirq); + + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); + + __clear_bit(hwirq, &value); + } + + chained_irq_exit(chip, desc); +} + +static int starfive_intc_probe(struct platform_device *pdev, struct device= _node *parent) +{ + struct device_node *intc =3D pdev->dev.of_node; + struct starfive_irq_chip *irqc; + struct reset_control *rst; + struct clk *clk; + int parent_irq; + int ret; + + irqc =3D kzalloc_obj(*irqc); + if (!irqc) + return -ENOMEM; + + irqc->base =3D of_iomap(intc, 0); + if (!irqc->base) { + pr_err("Unable to map registers\n"); + ret =3D -ENXIO; + goto err_free; + } + + rst =3D of_reset_control_get_exclusive(intc, NULL); + if (IS_ERR(rst)) { + pr_err("Unable to get reset control %pe\n", rst); + ret =3D PTR_ERR(rst); + goto err_unmap; + } + + clk =3D of_clk_get(intc, 0); + if (IS_ERR(clk)) { + pr_err("Unable to get clock %pe\n", clk); + ret =3D PTR_ERR(clk); + goto err_reset_put; + } + + ret =3D reset_control_deassert(rst); + if (ret) + goto err_clk_put; + + ret =3D clk_prepare_enable(clk); + if (ret) + goto err_reset_assert; + + raw_spin_lock_init(&irqc->lock); + + irqc->domain =3D irq_domain_create_linear(of_fwnode_handle(intc), STARFIV= E_INTC_SRC_IRQ_NUM, + &starfive_intc_domain_ops, irqc); + if (!irqc->domain) { + pr_err("Unable to create IRQ domain\n"); + ret =3D -EINVAL; + goto err_clk_disable; + } + + parent_irq =3D of_irq_get(intc, 0); + if (parent_irq < 0) { + pr_err("Failed to get main IRQ: %d\n", parent_irq); + ret =3D parent_irq; + goto err_remove_domain; + } + + irq_set_chained_handler_and_data(parent_irq, starfive_intc_irq_handler, + irqc); + + pr_info("Interrupt controller register, nr_irqs %d\n", + STARFIVE_INTC_SRC_IRQ_NUM); + + return 0; + +err_remove_domain: + irq_domain_remove(irqc->domain); +err_clk_disable: + clk_disable_unprepare(clk); +err_reset_assert: + reset_control_assert(rst); +err_clk_put: + clk_put(clk); +err_reset_put: + reset_control_put(rst); +err_unmap: + iounmap(irqc->base); +err_free: + kfree(irqc); + return ret; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(starfive_intc) +IRQCHIP_MATCH("starfive,jhb100-intc", starfive_intc_probe) +IRQCHIP_PLATFORM_DRIVER_END(starfive_intc) + +MODULE_DESCRIPTION("StarFive JHB100 External Interrupt Controller"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Changhuang Liang ");