From nobody Tue Jun 16 17:02:29 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1EC937419A; Thu, 30 Apr 2026 10:56:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777546606; cv=none; b=OTv5aJQKQ+aEk34spNnmgozk2gWlTa5cHqEoAwVYol4ZNzoeYheYQ3RcP4pva7j1Dz9QRdwUHCANodrFGM3RKrGaJiULmTsh8UJ0B6TH0Rikr8/3fa1Wvi1qvTxL2+Urgf1k1DqzxU9DiKUyzy6j21pjfliMZpIsS5lolEH3eVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777546606; c=relaxed/simple; bh=sF+1tIEd6BuztNNjDFDv9Tas7qjX2s1LXwwdN1iSsAQ=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=eESVG9NJZHwOITePJNtJhPUbZeGXY03FmDcmkN14hLsSn+w4OZrMmCUNNd0nzR/pbLVWxsgaU5+5nx4IhQpzfuKHAqT1TBsYwfNSkRw7YhJzSqNai3GYQqvUWs6BWqC+KRJ6PPg5uQYEE2BkRlNUa5yEyP7KWaAunQL5Vb90hHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kz3iuXW3; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cL+vmbET; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kz3iuXW3"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cL+vmbET" Date: Thu, 30 Apr 2026 10:56:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1777546603; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6yY/MlvtDm3Qq5KIg/Y6gF4bVDJQXYtzl90CA88IHXA=; b=kz3iuXW3UqM3FnJLmkdeG8ixmN0/Ye4Uc2Pm021N/9J0LW3XX9chPq24lCPOYjnhBpKoJV zFLuuko0HTpCZQ13XzitaPuArqmLPF38YDflJ+b7rAvSRNuASmD6sHRq07zatJrwY0Ksxl dI9/n3pGQETpvJN8aoo7mk9gR+5kqk8fDziqB4Iiq98xWIlvOXvpC0SQDO17TCYa4Z6rHr TaaMeWEVfBKekPT4rxWLBU5R9WWf/9rdm//eq0frMQgNBh+P+tHLrdfw/n0gAeZZdyO8OQ YJ7KUl1+JnRvIE1RVdFG4dGrvfq0ZncOg1YXRc40IZ/C9fUFvZ5WmtLJL9b34A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1777546603; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6yY/MlvtDm3Qq5KIg/Y6gF4bVDJQXYtzl90CA88IHXA=; b=cL+vmbETzhSRjg3yon9cW+K8HD6S2eRELj6ZXCRfbmSOPq8TCeacfh2N8iwbHXGafW2IAl hx/XdwexrMgGA2Bg== From: "tip-bot2 for Mason Huo" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/starfive: Increase the interrupt source number up to 64 Cc: Mason Huo , Changhuang Liang , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260416064751.632138-5-changhuang.liang@starfivetech.com> References: <20260416064751.632138-5-changhuang.liang@starfivetech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177754660198.3521451.4201283936339355050.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 5d1b12880fd878f315f41ac5dd19fd9fb476e7a0 Gitweb: https://git.kernel.org/tip/5d1b12880fd878f315f41ac5dd19fd9fb= 476e7a0 Author: Mason Huo AuthorDate: Wed, 15 Apr 2026 23:47:50 -07:00 Committer: Thomas Gleixner CommitterDate: Thu, 30 Apr 2026 12:53:05 +02:00 irqchip/starfive: Increase the interrupt source number up to 64 StarFive JHB100 SoC interrupt controller actually supports 64 interrupt sources, the original code only supported up to 32. now it is extended to 6= 4. Also use guard(raw_spinlock) to automatically release spinlocks. Signed-off-by: Mason Huo Signed-off-by: Changhuang Liang Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260416064751.632138-5-changhuang.liang@sta= rfivetech.com --- drivers/irqchip/irq-starfive-jhb100-intc.c | 47 ++++++++++++--------- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/i= rq-starfive-jhb100-intc.c index c33229b..b3d86bd 100644 --- a/drivers/irqchip/irq-starfive-jhb100-intc.c +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -19,10 +19,11 @@ #include #include =20 -#define STARFIVE_INTC_SRC0_CLEAR 0x10 -#define STARFIVE_INTC_SRC0_MASK 0x14 -#define STARFIVE_INTC_SRC0_INT 0x1c +#define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20)) +#define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20)) +#define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20)) =20 +#define STARFIVE_INTC_NUM 2 #define STARFIVE_INTC_SRC_IRQ_NUM 32 =20 struct starfive_irq_chip { @@ -54,19 +55,25 @@ static void starfive_intc_bit_clear(struct starfive_irq= _chip *irqc, static void starfive_intc_unmask(struct irq_data *d) { struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + int i, bitpos; =20 - raw_spin_lock(&irqc->lock); - starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); - raw_spin_unlock(&irqc->lock); + i =3D d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM; + bitpos =3D d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM; + + guard(raw_spinlock)(&irqc->lock); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos)); } =20 static void starfive_intc_mask(struct irq_data *d) { struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + int i, bitpos; + + i =3D d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM; + bitpos =3D d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM; =20 - raw_spin_lock(&irqc->lock); - starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_MASK, BIT(d->hwirq)); - raw_spin_unlock(&irqc->lock); + guard(raw_spinlock)(&irqc->lock); + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos)); } =20 static struct irq_chip intc_dev =3D { @@ -98,16 +105,19 @@ static void starfive_intc_irq_handler(struct irq_desc = *desc) =20 chained_irq_enter(chip, desc); =20 - value =3D ioread32(irqc->base + STARFIVE_INTC_SRC0_INT); - while (value) { - hwirq =3D ffs(value) - 1; + for (int i =3D 0; i < STARFIVE_INTC_NUM; i++) { + value =3D ioread32(irqc->base + STARFIVE_INTC_SRC_INT(i)); + while (value) { + hwirq =3D ffs(value) - 1; =20 - generic_handle_domain_irq(irqc->domain, hwirq); + generic_handle_domain_irq(irqc->domain, + hwirq + i * STARFIVE_INTC_SRC_IRQ_NUM); =20 - starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); - starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC0_CLEAR, BIT(hwirq)); + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(hwirq)); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(hwirq)); =20 - __clear_bit(hwirq, &value); + __clear_bit(hwirq, &value); + } } =20 chained_irq_exit(chip, desc); @@ -140,7 +150,8 @@ static int starfive_intc_probe(struct platform_device *= pdev, struct device_node=20 =20 raw_spin_lock_init(&irqc->lock); =20 - irqc->domain =3D irq_domain_create_linear(of_fwnode_handle(intc), STARFIV= E_INTC_SRC_IRQ_NUM, + irqc->domain =3D irq_domain_create_linear(of_fwnode_handle(intc), + STARFIVE_INTC_SRC_IRQ_NUM * STARFIVE_INTC_NUM, &starfive_intc_domain_ops, irqc); if (!irqc->domain) return dev_err_probe(&pdev->dev, -EINVAL, "Unable to create IRQ domain\n= "); @@ -155,7 +166,7 @@ static int starfive_intc_probe(struct platform_device *= pdev, struct device_node=20 irqc); =20 dev_info(&pdev->dev, "Interrupt controller register, nr_irqs %d\n", - STARFIVE_INTC_SRC_IRQ_NUM); + STARFIVE_INTC_SRC_IRQ_NUM * STARFIVE_INTC_NUM); =20 retain_and_null_ptr(irqc); return 0;