From nobody Tue Jun 16 17:02:29 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78DAE3BED31; Thu, 30 Apr 2026 10:56:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777546604; cv=none; b=rSLGEOh/iWHMUHzuDC0TTFYfye8j6JY3yef9mWfV0NP+xSsRteuFmX2Q1tktCNpBv+na3TiN1j7cSR/que5KUmtuyUtN16z0W40hUdmAiL7ghLIvui3T+rt0A4rS/puunylIs2fRq1lBF8BJ9AYbp0H9CgHlN3l184PcorWETjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777546604; c=relaxed/simple; bh=w4lyw93QXG7QqI5fMlNq6KtCFpFOuGqmyS5kRuhBZEk=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=LmBety0YA4m/GIa7H2nzy58py2d4zk60qgUJLCF9wqfudzbsNRAjCk1b/RJ30h6SFwr6slXXJsDNcEl69X29kddoyB+vj9SXNNe8NEwiwvpfgKi3br75NFOJheDP4AC4C0ZVQHIt87jP5n5ZwVPGPCvU5+vbNrAaUSFePruC6TY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Dlmtt+ab; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RuJnLZsg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Dlmtt+ab"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RuJnLZsg" Date: Thu, 30 Apr 2026 10:56:40 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1777546602; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w5uSN2A7CLYLT12/H/ZlxkjhXCuNas5/EqmdjdpKcZg=; b=Dlmtt+ab8jQwvJZTvSp2xlESuV/GbZNJ48vwHZ/egq5F72SNuBc2x9L7utBZO/b1WobQNt 742E70PL+hn+YMujzNS4ANJCgvaMN859P3SjitqNaNsbEGo0QMzfgjXihp2P+robDsmHz3 A3VhoTbVdA1IsBVTkB9QNYtAw04ZHzfoYR7P3EsKzqiSx3uXdkjR3Po9Y/qvrTfr7foPgI pgsFW7btaqsQEJkDPukMewLwa6ZQy6pnpJHv47FK5WIrr7frBL21jHDHfq5x8ORdUoOjQg M/TEEmWzd/DFriEw41d0d79zNAfXZLMMKm8rUleccN+6SUfLfrBL82d4mIKzrQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1777546602; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w5uSN2A7CLYLT12/H/ZlxkjhXCuNas5/EqmdjdpKcZg=; b=RuJnLZsgnKdyIUFr0Ol+VzPoguulL4dXkXadVCQbkPSPl+Sm4PpTxrt4tFkz0wxWS0IocP +/duOXlrKghnhjAQ== From: "tip-bot2 for Changhuang Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks Cc: Changhuang Liang , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260416064751.632138-6-changhuang.liang@starfivetech.com> References: <20260416064751.632138-6-changhuang.liang@starfivetech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <177754660077.3521451.4510944624806069339.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 96c0c9b488502c89e91f32353b853422a45a1646 Gitweb: https://git.kernel.org/tip/96c0c9b488502c89e91f32353b853422a= 45a1646 Author: Changhuang Liang AuthorDate: Wed, 15 Apr 2026 23:47:51 -07:00 Committer: Thomas Gleixner CommitterDate: Thu, 30 Apr 2026 12:53:06 +02:00 irqchip/starfive: Implement irq_set_type() and irq_ack() callbacks Add irq_set_type() callback to support configuring interrupt trigger types (level high/low, edge rising/falling) for the JHB100 interrupt controller. Also add irq_ack() callback as required by handle_edge_irq(). Signed-off-by: Changhuang Liang Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260416064751.632138-6-changhuang.liang@sta= rfivetech.com --- drivers/irqchip/irq-starfive-jhb100-intc.c | 73 +++++++++++++++++++++- 1 file changed, 73 insertions(+) diff --git a/drivers/irqchip/irq-starfive-jhb100-intc.c b/drivers/irqchip/i= rq-starfive-jhb100-intc.c index b3d86bd..0d59148 100644 --- a/drivers/irqchip/irq-starfive-jhb100-intc.c +++ b/drivers/irqchip/irq-starfive-jhb100-intc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -19,12 +20,20 @@ #include #include =20 +#define STARFIVE_INTC_SRC_TYPE(n) (0x04 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20)) #define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20)) =20 +#define STARFIVE_INTC_TRIGGER_MASK 0x3 +#define STARFIVE_INTC_TRIGGER_HIGH 0 +#define STARFIVE_INTC_TRIGGER_LOW 1 +#define STARFIVE_INTC_TRIGGER_POSEDGE 2 +#define STARFIVE_INTC_TRIGGER_NEGEDGE 3 + #define STARFIVE_INTC_NUM 2 #define STARFIVE_INTC_SRC_IRQ_NUM 32 +#define STARFIVE_INTC_TYPE_NUM 16 =20 struct starfive_irq_chip { void __iomem *base; @@ -32,6 +41,16 @@ struct starfive_irq_chip { raw_spinlock_t lock; }; =20 +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32 reg, u32= mask, u32 data) +{ + u32 value; + + value =3D ioread32(irqc->base + reg) & ~mask; + data &=3D mask; + data |=3D value; + iowrite32(data, irqc->base + reg); +} + static void starfive_intc_bit_set(struct starfive_irq_chip *irqc, u32 reg, u32 bit_mask) { @@ -76,10 +95,64 @@ static void starfive_intc_mask(struct irq_data *d) starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos)); } =20 +static void starfive_intc_ack(struct irq_data *d) +{ + /* for handle_edge_irq, nothing to do */ +} + +static int starfive_intc_set_type(struct irq_data *d, unsigned int type) +{ + struct starfive_irq_chip *irqc =3D irq_data_get_irq_chip_data(d); + u32 i, bitpos, ty_pos, ty_shift, trigger, typeval; + irq_flow_handler_t handler; + + i =3D d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM; + bitpos =3D d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM; + ty_pos =3D bitpos / STARFIVE_INTC_TYPE_NUM; + ty_shift =3D (bitpos % STARFIVE_INTC_TYPE_NUM) * 2; + + switch (type) { + case IRQF_TRIGGER_LOW: + trigger =3D STARFIVE_INTC_TRIGGER_LOW; + handler =3D handle_level_irq; + break; + case IRQF_TRIGGER_HIGH: + trigger =3D STARFIVE_INTC_TRIGGER_HIGH; + handler =3D handle_level_irq; + break; + case IRQF_TRIGGER_FALLING: + trigger =3D STARFIVE_INTC_TRIGGER_NEGEDGE; + handler =3D handle_edge_irq; + break; + case IRQF_TRIGGER_RISING: + trigger =3D STARFIVE_INTC_TRIGGER_POSEDGE; + handler =3D handle_edge_irq; + break; + default: + return -EINVAL; + } + + irq_set_handler_locked(d, handler); + typeval =3D trigger << ty_shift; + + guard(raw_spinlock)(&irqc->lock); + + starfive_intc_mod(irqc, STARFIVE_INTC_SRC_TYPE(i) + 4 * ty_pos, + STARFIVE_INTC_TRIGGER_MASK << ty_shift, typeval); + + /* Once the type is updated, clear interrupt can help to reset the type v= alue */ + starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos)); + starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos)); + + return 0; +} + static struct irq_chip intc_dev =3D { .name =3D "StarFive JHB100 INTC", .irq_unmask =3D starfive_intc_unmask, .irq_mask =3D starfive_intc_mask, + .irq_ack =3D starfive_intc_ack, + .irq_set_type =3D starfive_intc_set_type, }; =20 static int starfive_intc_map(struct irq_domain *d, unsigned int irq,